Flyback Converter Control for Transistor Turn-On Voltage Valleys
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Solution Overview
Problem
Conventional fly-back quasi-resonant switch-mode power converters experience high switching losses due to a high voltage drop at which the transistor is turned on, especially at high input voltages.
Innovation Solution
A controller for a power converter that includes a first gate driver, one or more voltage detectors, a time controller, and a second gate driver, which detect and adjust voltage drops across transistors by determining the time duration for the second drive signal to remain at a logic high level based on the detected voltage drops.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If the transistor is turned on at high input voltage to maintain power conversion capability, then the power conversion function is maintained, but the voltage drop across the transistor increases causing higher switching losses
Solution Approach 1:
The controller detects the voltage drop across the transistor before the switching operation and adjusts the drive signal timing in advance. By performing this detection and adjustment beforehand, the system prepares the transistor for optimal switching conditions, reducing the voltage drop at the moment of turn-on and thereby minimizing switching losses without compromising power conversion capability
Solution Approach 2:
The system implements a feedback mechanism where the controller continuously monitors the voltage drop across the transistor during operation. Based on this real-time feedback, the controller dynamically adjusts the drive signal parameters to maintain optimal switching conditions, ensuring that the transistor operates with minimal voltage drop even at high input voltages, thus reducing switching losses
2Reliability
If the drive signal time duration is extended to ensure complete switching, then the switching reliability is improved, but the switching loss increases due to prolonged voltage drop
Solution Approach 1:
The system dynamically adjusts the drive signal time duration based on real-time detection of the transistor's voltage drop characteristics. Rather than using a fixed time duration, the controller modifies the drive signal timing adaptively, extending it only as much as necessary to ensure complete switching while minimizing the period during which voltage drop occurs, thus balancing reliability improvement with loss reduction
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The proposed solution effectively reduces the switching loss of the quasi-resonant switch-mode power converter by optimizing the time duration for the second drive signal, thereby minimizing the voltage drop across the transistor at turn-on.
Implementation Method 1
The parasitic capacitor 152 and the primary winding 112 are parts of an LC resonant circuit... the parasitic capacitor 152 and the primary winding 112 start going through a resonance process, during which the voltage drop from the drain terminal 154 to the source terminal 158 of the transistor 150 changes between a peak magnitude and a valley magnitude
Data Source
AI summary
Controller and method for a power converter. For example, a controller for a power converter includes: a first gate driver configured to output a first drive signal to a first transistor related to a primary winding, the first transistor including a drain terminal and a source terminal, the primary winding being configured to receive an input voltage, the primary being coupled to a first auxiliary winding and a second auxiliary winding; one or more voltage detectors configured to generate a first detection signal and a second detection signal based at least in part on a current signal related to the first auxiliary winding; a time controller configured to receive the first detection signal and the second detection signal and generate a control signal based at least in part on the first detection signal and the second detection signal; and a second gate driver configured to receive the control signal.