Fly-by Bus Signal Order for Memory Chip Ring-back Margin
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
In semiconductor devices using a fly-by topology, signal integrity is compromised due to signal distortion and ring-back phenomena, which are difficult to address without increasing the physical distance between memory chips, thereby affecting the downsizing of memory devices or storage devices.
Innovation Solution
The semiconductor device rearranges the order in which electrical signals are supplied to memory chips via a bus, extending bus lengths between certain nodes without increasing physical distances, thereby securing a ring-back margin and enhancing signal integrity while maintaining device downsizing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the physical distance between memory chips is increased to address signal distortion and ring-back phenomena, then signal integrity is improved, but device size increases
Solution Approach 1:
The patent inverts the conventional approach by not increasing physical distance to improve signal integrity, but instead changing the signal transmission order (bus path) to achieve the same goal. The bus path is configured to supply signals to memory chips in a sequence different from their physical arrangement, thereby improving signal integrity without increasing device size.
Solution Approach 2:
The patent changes the parameter of signal transmission sequence rather than physical distance. By configuring the bus to transmit signals in a specific order (first to third memory chip, then second memory chip), the system modifies the temporal and path-based parameters to improve signal integrity while maintaining compact physical layout.
2Reliability
If the bus path order is changed to improve signal integrity, then ring-back margin is increased, but bus routing complexity increases
Solution Approach 1:
The bus is segmented into multiple paths with different transmission orders for different memory chip regions. The first bus supplies signals to the first memory chip region in a specific sequence, while the second bus supplies signals to the second memory chip region in a different sequence. This segmentation allows independent optimization of signal integrity for each region without requiring complete redesign of the entire bus system.
Solution Approach 2:
Different bus paths are assigned different transmission sequences tailored to the specific arrangement and requirements of each memory chip region. The first bus uses one transmission order for the first memory chip region, while the second bus uses a different transmission order for the second memory chip region, optimizing signal integrity locally for each region without affecting the entire system.
Data Source
AI summary
A semiconductor device includes a plurality of memory chips arranged in a line on a substrate, and a bus connected to the plurality of memory chips and configured to sequentially supply an electrical signal to the plurality of memory chips in accordance with a fly-by topology. An order in which the electrical signal is supplied to the plurality of memory chips is different from an order in which the plurality of memory chips is arranged in the line on the substrate.