Flying-Adder Clock Synthesis for Instant Digital Frequency Control
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Solution Overview
Problem
Existing clock signal generation techniques, particularly Phase Lock Loops (PLLs), face limitations in frequency synthesisability, design complexity, and response speed, which are not instantaneous, making them challenging for modern electronic devices, especially large System-on-Chip (SoC) integrated circuits.
Innovation Solution
The introduction of the Flying-Adder architecture and the concept of time-average-frequency lead to the development of a fixed-VCO-Flying-Adder architecture, enabling the creation of a Digital-to-Frequency Converter (DFC) that simplifies clock signal generation by allowing non-repetitive cycles and providing instantaneous frequency control through digital modulation, reducing design complexity and enhancing spread spectrum capabilities.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If Phase Lock Loop (PLL) is used for clock signal generation, then frequency synthesis capability is provided, but design complexity increases and response speed becomes non-instantaneous
Solution Approach 1:
The patent replaces the traditional analog PLL mechanism with a digital Flying-Adder architecture. Instead of using analog phase detectors, charge pumps, and voltage-controlled oscillators, the invention employs digital counters, adders, and programmable logic to achieve frequency synthesis. This substitution of analog mechanical/electrical systems with digital logic circuits reduces design complexity while maintaining frequency synthesis capability and enabling instantaneous response to frequency changes.
2Adaptability or versatility
If Phase Lock Loop (PLL) is used for clock signal generation, then frequency synthesis capability is provided, but response speed is not instantaneous
Solution Approach 1:
The Flying-Adder architecture implements dynamic frequency switching by using programmable counter values and digital control logic. When frequency changes are required, the system immediately updates the counter reload values and control registers, enabling instantaneous frequency transitions without the gradual phase adjustment required by analog PLLs. This dynamic digital control allows the system to adapt frequency synthesis requirements in real-time with immediate response.
3Reliability
If traditional clock generation architecture is used, then clock signals are generated, but spread spectrum performance is limited
Solution Approach 1:
The patent merges the frequency synthesis function with spread spectrum modulation capabilities within the single Flying-Adder architecture. By integrating the counter-based frequency generation with digital modulation logic that can apply pseudorandom sequences to the clock signal, the system achieves both frequency synthesis and spread spectrum performance without requiring separate analog modulation circuits. This consolidation improves spread spectrum performance while avoiding the additional complexity of separate modulation stages.
Data Source
AI summary
To make Flying-Adder architecture even more powerful, a new concept, time-average-frequency, is incorporated into the clock generation circuitry. This is a fundamental breakthrough since it attacks the clock generation problem from its root: how is the clock signal used in real systems? By investigating from this direction, a much more powerful architecture, fixed-VCO-Flying-Adder architecture, is created. Furthermore, based on fixed-VCO-Flying-Adder frequency synthesizer and time-average-frequency, a new type of component called Digital-to-Frequency Converter (DFC) is born.