FMOM Capacitor Multi-Level Interconnect Design
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Solution Overview
Problem
Conventional finger metal-oxide-metal (FMOM) capacitors in advanced CMOS technologies have low capacitance values, failing to meet circuit design specifications for de-coupling capacitors within a small device footprint.
Innovation Solution
The introduction of super-via structures that couple interconnect layers more than one level apart, specifically between M1 and M3 levels, along with an interdigitated design of conductive fingers at different interconnect levels, to increase capacitance without expanding the device footprint.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If conventional FMOM structures are used, then the device footprint remains small, but the capacitance value is low and does not satisfy circuit design specifications
Solution Approach 1:
The patent extends the capacitor structure from a single interconnect level to multiple interconnect levels (Mx, Mx-1, Mx-2, Mx-3), utilizing the vertical dimension to increase capacitance. By stacking conductive fingers across four different interconnect levels and connecting them through vias, the effective capacitance area is multiplied without increasing the lateral footprint, achieving approximately 260% increased capacitance within the same device area.
Solution Approach 2:
The patent implements nested interdigitated finger structures where conductive fingers at different interconnect levels are interlaced with each other. The first and second sets of conductive fingers at Mx level are nested with third and fourth sets at Mx-1 level, which are in turn nested with fifth and sixth sets at Mx-2 level, and seventh and eighth sets at Mx-3 level. This nested arrangement maximizes the overlapping area between conductive plates while maintaining a compact footprint.
2Quantity of substance
If additional materials are added to increase capacitance, then the capacitance value improves, but the manufacturing complexity and cost increase
Solution Approach 1:
The patent reuses existing conductive finger structures and interconnect materials that are already part of the standard CMOS fabrication process. The same conductive materials and deposition techniques used for creating interconnect wires are utilized to form the capacitor fingers, eliminating the need for specialized materials or additional processing steps. The vias connecting different levels also use standard via formation processes, keeping the manufacturing complexity aligned with conventional FMOM structures.
Data Source
AI summary
A capacitor includes first conductive fingers interdigitated with second conductive fingers at an Mx interconnect level, and third conductive fingers interdigitated with fourth conductive fingers at an Mx-1 interconnect level. The third conductive fingers are offset from the first conductive fingers. The second conductive fingers are offset from the fourth conductive fingers. The capacitor further includes fifth conductive fingers interdigitated with sixth conductive fingers at an Mx-2 interconnect level. The fifth conductive fingers are offset from the third conductive fingers. The sixth conductive fingers are offset from the fourth conductive fingers. The capacitor further includes seventh conductive fingers interdigitated with eighth conductive fingers at an Mx-3 interconnect level. The seventh conductive fingers are offset from the fifth conductive fingers. The eighth conductive fingers are offset from the sixth conductive fingers. A first set of vias electrically couples the first conductive fingers to the fifth conductive fingers.