Folded Crossbar Array Circuit for Vector-Matrix Multiplication
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Solution Overview
Problem
Conventional crossbar array circuits face pitch mismatch issues between interface devices and crossbar devices, leading to scalability limitations and increased parasitic effects, which hinder efficient vector-matrix multiplications and accuracy in large-scale computations.
Innovation Solution
The implementation of folded crossbar array circuits with accordion-style folding and access controls, allowing for flexible layout designs that reduce pitch mismatch and parasitic impacts, enabling the storage of larger weight matrices and improved scalability through the use of multiple folds and a ramping circuit for consistent signal transmission.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional crossbar array circuits are used, then the circuit structure is simple, but pitch mismatch issues occur between interface devices and crossbar devices
Solution Approach 1:
The crossbar array is divided into multiple folded column circuits, where each folded column circuit is further segmented into multiple portions (first, second, third columns). This segmentation allows independent pitch optimization for each segment while maintaining overall array functionality, resolving the pitch mismatch between interface devices and crossbar devices.
Solution Approach 2:
The patent introduces a folding dimension to the traditional planar crossbar array layout. By folding columns in an accordion style and connecting portions through additional metal traces, the design transforms a 2D pitch matching problem into a 3D spatial arrangement, enabling pitch optimization without increasing device complexity.
2Productivity
If the crossbar array size is increased for larger computations, then computational capability is improved, but parasitic effects increase
Solution Approach 1:
By segmenting the large crossbar array into multiple folded column circuits with controlled portions, the patent reduces the effective signal path length within each segment. This segmentation limits the accumulation of parasitic effects while maintaining the overall computational capability through parallel operation of multiple folded columns.
Solution Approach 2:
The folding architecture redistributes crossbar devices across multiple spatial layers and metal trace levels. This dimensional transformation reduces the physical distance between distant crossbar devices and their corresponding interface devices, thereby reducing parasitic resistance and capacitance effects even in large-scale arrays.
3Adaptability or versatility
If the number of ADCs is reduced for scalability, then device count is decreased, but the ability to handle total columns is compromised
Solution Approach 1:
Each folded column circuit is designed to be universally compatible with a single ADC through standardized interface connections. The folding architecture allows one ADC to service multiple folded column circuits by sequentially or parallelly accessing different portions, enabling the system to handle more columns than the number of ADCs would suggest.
Solution Approach 2:
The patent implements periodic access patterns where a single ADC cycles through multiple folded column circuits in sequence. By folding columns and using time-multiplexed access, the system achieves column handling capability greater than the number of ADCs, improving scalability while maintaining adequate computational throughput.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The folded crossbar array design effectively addresses pitch mismatch and parasitic effects, enhancing scalability and flexibility for larger vector-matrix multiplications, reducing errors, and allowing for more efficient storage and processing of weight matrices with reduced power consumption.
Implementation Method 1
The resistance of a RRAM may be electrically switched between two states: a High-Resistance State (HRS) and a Low-Resistance State (LRS).
Data Source
AI summary
Technologies relating to folded crossbar array circuits and methods for reducing pitch match issues within folded crossbar array circuits and increasing the scalability of folded crossbar array circuits are disclosed. An example crossbar array circuit includes: a first folded column circuit folded as at least two portions; a first ADC; a first plurality of DACs; and a first plurality of access controls, wherein the first folded column circuit connected to the first ADC, the first plurality of DACs, and the first plurality of access controls. In some implementations, the three portions comprises a first column of crossbar devices, a second column of crossbar devices, and a third column of crossbar devices, and wherein the first column of crossbar devices, the second column of crossbar devices, and the third column of crossbar devices are configured to be controlled by the first plurality of access controls.