Folded Stacked Planar Capacitors for Dense 1TnC Memory Cells
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Solution Overview
Problem
Conventional non-volatile memories, such as MRAM, NAND, and NOR flash, are not suitable for low-power and compact computing devices due to high write energy, low density, and high power consumption, and traditional ferroelectric memories suffer from charge degradation and disturbance issues.
Innovation Solution
The use of stacked and folded capacitor configurations in memory bit-cells, combined with word-line boosting and refresh mechanisms, to mitigate charge disturbance and enhance memory endurance, while also optimizing capacitor placement to reduce area occupancy and parasitic capacitance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional non-volatile memories (MRAM, NAND, NOR flash) are used, then data retention is achieved, but write energy consumption is high and density is low
Solution Approach 1:
The memory system is divided into multiple banks (first bank, second bank, third bank) that can be independently managed. Each bank contains multiple bitcells with capacitors that can be selectively refreshed or maintained, allowing energy-efficient operation by only activating necessary segments rather than the entire memory array.
Solution Approach 2:
The patent employs different voltage levels (first voltage, second voltage, third voltage) for different operational modes. Word lines are boosted to higher voltages during write operations to overcome threshold effects, while read operations use lower voltages. The capacitors operate at different voltage states (first state, second state, third state) to represent binary data, enabling low-power storage without continuous refresh.
2Area of stationary object
If memory dimensions are reduced to increase density, then area is reduced, but capacitor placement becomes more challenging
Solution Approach 1:
The patent transitions from planar capacitor layouts to three-dimensional stacked capacitor structures. Multiple capacitors are vertically stacked above each other, with bottom electrodes, dielectric layers, and top electrodes arranged in multiple levels. This vertical stacking enables significantly higher density within the same footprint area while maintaining manufacturability through standard semiconductor fabrication processes.
Solution Approach 2:
The capacitor structure employs nested layers where bottom electrodes are surrounded by dielectric material, which is in turn surrounded by top electrodes. Multiple such capacitor units are nested vertically, with each capacitor containing the previous one or adjacent to it in the vertical dimension. This nested arrangement maximizes space utilization and simplifies routing by sharing common electrodes and interconnect structures.
3Quantity of substance
If multiple capacitors are used in memory bit-cells, then storage capacity increases, but area occupancy increases
Solution Approach 1:
Instead of placing multiple capacitors side-by-side in the planar direction, the patent stacks capacitors vertically in the third dimension. Each bitcell contains multiple stacked capacitors that share common bottom electrodes and are connected through vertical interconnects. This approach maintains high storage capacity per unit area by utilizing vertical space rather than horizontal space.
Solution Approach 2:
Multiple capacitors within each bitcell share common electrodes and interconnect structures. The bottom electrodes of stacked capacitors are merged into a single continuous structure, and top electrodes are connected through shared wiring. This merging reduces the total area required compared to having completely separate capacitor structures, while still providing multiple storage nodes per bitcell.
4Area of stationary object
If capacitor size is reduced to increase density, then area is reduced, but parasitic capacitance becomes more significant
Solution Approach 1:
The patent employs different dielectric materials with different properties in different regions of the capacitor structure. High-k dielectric materials are used in specific layers to maximize capacitance density, while low-loss dielectric materials are used in other regions to minimize parasitic effects. The electrode structures are also locally optimized with different materials and geometries to reduce parasitic resistance and capacitance in critical areas while maintaining high capacitance where needed.
Data Source
AI summary
A configuration for efficiently placing a group of capacitors with one terminal connected to a common node is described. The capacitors are stacked and folded along the common node. In a stack and fold configuration, devices are stacked vertically (directly or with a horizontal offset) with one terminal of the devices being shared to a common node, and further the capacitors are placed along both sides of the common node. The common node is a point of fold. In one example, the devices are capacitors. N number of capacitors can be divided in L number of stack layers such that there are N/L capacitors in each stacked layer. The N/L capacitors are shorted together with an electrode (e.g., bottom electrode). The electrode can be metal, a conducting oxide, or a combination of a conducting oxide and a barrier material. The capacitors can be planar, non-planar or replaced by memory elements.