Fork Sheet Nanosheet Structure for Dielectric Pillar Electrostatics
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Solution Overview
Problem
Conventional fork sheet devices experience weaker electrostatic control close to the dielectric pillar, leading to poor gate control, especially at small gate lengths.
Innovation Solution
A semiconductor structure with improved electrostatic contact near the dielectric pillar, featuring a dielectric pillar between vertical nanosheet stacks and horizontal dielectric bridge structures connecting the nanosheets to the dielectric pillar, with a dielectric spacer surrounding the lower portion of the pillar.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If a dielectric pillar is introduced to physically isolate pFET and nFET nanosheet devices, then area scalability and device density are improved, but electrostatic control close to the dielectric pillar deteriorates
Solution Approach 1:
The patent applies local quality by introducing horizontal dielectric bridge structures specifically at the locations where nanosheets contact the dielectric pillar, rather than uniformly modifying the entire structure. These localized bridge structures provide enhanced electrostatic control precisely at the problematic regions near the dielectric pillar, while maintaining the overall compact design and area scalability benefits of the fork sheet architecture.
Solution Approach 2:
The horizontal dielectric bridge structures act as intermediary elements between the nanosheets and the dielectric pillar. These bridge structures mediate the electrostatic interaction, providing improved gate control and electrostatic confinement in the critical regions where nanosheets meet the dielectric pillar, thus resolving the electrostatic control deterioration caused by the dielectric pillar's presence.
2Area of stationary object
If n-to-p spacing is reduced to improve area scalability, then device density increases, but gate control deteriorates due to weaker electrostatic control
Solution Approach 1:
The horizontal dielectric bridge structures are locally positioned at the interfaces between nanosheets and the dielectric pillar, providing enhanced electrostatic control precisely where needed. This localized enhancement allows for reduced n-to-p spacing while maintaining adequate gate control through the targeted electrostatic reinforcement at critical locations rather than requiring uniform spacing increases.
3Area of stationary object
If fork sheet structure is used instead of GAA structure, then area scalability is improved, but electrostatic control close to dielectric pillar is weakened
Solution Approach 1:
The horizontal dielectric bridge structures serve as intermediary elements that compensate for the inherent electrostatic control weaknesses in the fork sheet architecture near the dielectric pillar. These bridge structures mediate the electrostatic field distribution, providing enhanced control in the critical regions without requiring a transition to the more complex GAA structure, thus maintaining area scalability while improving electrostatic performance.
Solution Approach 2:
The patent modifies the electrostatic parameters in the critical regions by introducing horizontal dielectric bridge structures that change the electric field distribution and capacitance characteristics near the dielectric pillar. This parameter change enhances electrostatic control locally, allowing the fork sheet structure to achieve performance comparable to or better than conventional structures while maintaining its area scalability advantages.
Data Source
AI summary
A semiconductor structure is provided having improved electrostatic contact close to the dielectric pillar that separates a first device region from a second device region. The semiconductor structure includes a dielectric pillar located between a first vertical nanosheet stack of suspended semiconductor channel material nanosheets and a second vertical nanosheet stack of suspended semiconductor channel material nanosheets. Horizontal dielectric bridge structures can be located in the first and second device regions. The horizontal bridge structures connect each of the suspended semiconductor channel material nanosheets to a respective sidewall of the dielectric pillar. A dielectric spacer structure can laterally surround a lower portion of the dielectric pillar and be present in a semiconductor substrate. In some embodiments, the horizontal dielectric bridge structures can be omitted.