Nanoinformatics TRIZ Cases
- Self-Aligned Inner Spacer for Smooth GAA Source/Drain Epitaxy
Reflowed inner spacers smooth the GAA source/drain interface, improving epitaxial growth quality and reducing interface defects.
- Thin Dummy Sidewall Spacers for Reduced-Pitch Transistors
Metal-containing dummy spacers and hard masks preserve epitaxy growth selectivity at very small thicknesses, enabling reduced transistor pitch.
- Self-Aligned Gate Separation Structure for Consistent Gate Width
A preformed gate separation substructure guides gate cutting to keep gate widths consistent and improve transistor reliability at high integration.
- Ferroelectric Heterojunction for Wide-Range Low-Power Optical Sensing
An HZO/α-In2Se3 heterojunction combines optical sensing, processing, and memory to detect wide-range weak light with lower power and smaller size.
- Multi-Gate FET Qubit Layout for Stable Quantum Dot Confinement
Orthogonal primary and secondary gates confine quantum dots with larger energy spacing, improving qubit stability and 3D integration.
- Stacked Channel MOSFET Structure for Scaled Device Reliability
Vertically stacked channel patterns preserve MOSFET scaling while improving electrical characteristics, connectivity, and reliability.
- Forksheet Dielectric Wall Layout for Channel Stress Transfer
Segmented dielectric wall protrusions deform under source/drain stress, improving channel stress transfer and carrier mobility in Forksheet structures.
- Thin Dummy Sidewall Spacers for Reduced-Pitch Transistor Epitaxy
A metal-containing dummy spacer keeps epitaxial growth selective at reduced thickness, enabling tighter transistor pitch in nano-structure devices.
- Nanorod LED Structure With Porous Layer for Light Extraction
A porous semiconductor layer and sidewall passivation help nanorod LEDs maintain luminous efficiency as LED size shrinks to micro and nano scales.
- Nanorod LED Structure With Porous Layer for Luminous Efficiency
A porous semiconductor layer with voids relieves stress in nanorod LEDs, helping preserve luminous efficiency at nano-scale diameter.
- Backside Contact Extension Region for Lower-Resistance BEOL Wiring
An extended backside contact adds lateral connection area to cut interfacial resistance, ease wire alignment, and reduce BEOL shorting risk.
- Ferroelectric Heterojunction Structure for In-Sensor Optical Memory
A ferroelectric HZO and α-In2Se3 heterojunction combines light sensing, signal processing, and memory to cut sensor size and power use.
- Semiconductor Isolation Structure for Short-Channel Suppression
Different-height isolation layers and surrounding gates suppress short channel effects and punch-through while improving carrier mobility on bulk silicon.
- Inter-Sheet Filler Layer for Multi-Patterned Metal Gate Threshold Control
An inter-sheet filler layer blocks gate metal in selected nanostructures, preserving gate dielectric integrity and enabling distinct threshold voltages.
- Backside Power Rail Formation with PAI for Leakage-Free Contacts
Pre-amorphous implantation enables uniform wet removal of the semiconductor layer, forming backside contacts without plug damage or leakage paths.
- Vertical DRAM Cell Structure With Air Gaps for Low-Parasitic Scaling
Air gaps between word lines and stacked vertical cells help this DRAM layout cut parasitic capacitance while preserving density and cycle time.
- Fork Sheet Nanosheet Structure for Dielectric Pillar Electrostatics
Horizontal dielectric bridges reinforce electrostatic control near the dielectric pillar, preserving gate control as fork sheet spacing shrinks.
- Stacked GAA FET Bottom Contact for Self-Aligned Current Control
A self-aligned bottom contact reaches the n-type epitaxial sidewall in a stacked GAA FET, improving current control while reducing variability.
- FinFET Air-Gap Gate Spacer Structure for Lower Parasitic Capacitance
Air gaps sealed beside gate spacers and around fins cut parasitic capacitance, reducing RC delay and preserving IC scaling.
- Hybrid-Fin Gate Structure for Easier Dummy Gate Replacement
A small-footing dummy gate wrapped around nanostructures expands the replacement-gate window, eases removal, and helps prevent voids.
- Silicon-28 Superlattice Epitaxy for Higher Carrier Mobility
A silicon-28 superlattice with constrained non-semiconductor monolayers boosts carrier mobility and blocks dopant diffusion to reduce defects.
- Active Region Cut-Mask Layout for Corner-Rounding Removal
A gate overlapping the out-corner edge guides cut-mask patterning to remove corner rounding in different-width active regions.
- Source/Drain Contact Stack With Plasma Cleaning for Low Resistance
Plasma cleaning removes oxygen compounds at the source/drain contact interface, lowering resistance and enabling thinner barrier layers.
- Source/Drain Contact Structure With Isotropic Etching for TDDB Isolation
Isotropic etching separates dense and isolated source/drain contact regions to increase spacing and improve TDDB reliability.
- Punch-Through Stopper Ion Implantation for GAA Transistors
Source/drain cavity ion implantation forms a punch-through stopper in GAA transistors to block dopant diffusion, cut leakage, and improve DC and AC performance.
- GAA Transistor Source/Drain Adhesion Layer for Epitaxial Continuity
An adhesion layer in the source/drain trench enables continuous epitaxy in GAA transistors, improving short-channel control and leakage.
- Backside Trench Gate Isolation in Nanosheet Integrated Circuits
Backside trench etching isolates nanosheet transistor gate electrodes without extra photolithography, improving density, yield, and performance.
- Non-Conformal Gate Dielectric Layout for Multi-Vt GAA Nanosheets
Asymmetric gate dielectric thickness protects GAA nanosheets during etching and enables multiple threshold voltages without harming reliability.
- Wafer Bonding Humidity Control for Nano-FET Substrate Quality
Controlling relative humidity during wafer bonding reduces edge bubbles and non-bonded edges, improving substrate quality for nano-FETs.
- Multi-Gate GAA FET Seed Layer Layout for Defect-Free Epitaxy
Sidewall semiconductor seed layers enlarge the epitaxy surface in GAA FET trenches, reducing source/drain defects while preserving gate isolation.
- Nanowire GAA Transistor Structure to Reduce Voids and Short-Channel Effects
A nanowire gate-all-around structure uses selective layer removal and self-aligned formation to cut voids and short-channel effects.
- Quantum Dot Cavity Epitaxy for Precise Positioning
A two-step cavity epitaxy sequence improves quantum dot placement and lattice matching for scalable single-photon semiconductor structures.