GAA Transistor Source/Drain Adhesion Layer for Epitaxial Continuity
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing techniques for fabricating gate-all-around (GAA) transistors face challenges due to the scaling down of semiconductor IC dimensions, leading to discontinuous source/drain layers and issues with short-channel control, sub-threshold leakage, and parasitic capacitance.
Innovation Solution
The introduction of an adhesion layer within the source/drain region, which bonds to both Si channel layer surfaces and SiN inner spacer layer surfaces, provides a uniform base layer for subsequent source/drain epitaxial layer growth, ensuring continuity and overcoming the epitaxial merge issue.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional fabrication techniques are used for GAA transistors, then manufacturing process simplicity is maintained, but discontinuous source/drain layers form leading to poor short-channel control and high sub-threshold leakage
Solution Approach 1:
An adhesion layer is introduced as an intermediary between the Si channel layer and the source/drain epitaxial layer. This adhesion layer serves as a mediator that promotes continuous epitaxial growth by bonding to both the Si channel layer surfaces and the SiN inner spacer layer surfaces, thereby resolving the discontinuity issue without fundamentally changing the overall fabrication process flow
Solution Approach 2:
The adhesion layer is deposited in advance before the source/drain epitaxial layer formation. This preliminary action prepares the surface by creating a uniform base layer that ensures continuous epitaxial growth, preventing the formation of discontinuous layers that would occur with conventional direct growth methods
2Manufacturing precision
If conventional fabrication techniques are used for GAA transistors, then process simplicity is maintained, but epitaxial merge issues occur resulting in discontinuous source/drain layers
Solution Approach 1:
The adhesion layer acts as a mediator that facilitates the merging of epitaxial layers from adjacent fins. By bonding to both Si channel layer surfaces and SiN inner spacer layer surfaces, it creates a continuous growth path that enables the epitaxial layers to merge properly, eliminating the discontinuity problem
Solution Approach 2:
The deposition of the adhesion layer changes the surface properties and chemical composition of the growth interface. This parameter change in the surface layer enables continuous epitaxial growth by providing appropriate bonding sites and a uniform surface for the source/drain material to grow continuously across the fin structures
3Reliability
If conventional fabrication techniques are used for GAA transistors, then manufacturing simplicity is maintained, but sub-threshold leakage increases due to discontinuous source/drain layers
Solution Approach 1:
The adhesion layer serves as a mediator that ensures continuous source/drain layer formation by bonding to the Si channel layer and SiN inner spacer layer. This continuity eliminates the leakage paths that would exist with discontinuous layers, thereby reducing sub-threshold leakage without requiring complex device structures
Solution Approach 2:
By changing the surface properties through adhesion layer deposition, the electrical characteristics of the source/drain region are improved. The continuous layer formed over the adhesion layer provides better electrical confinement and reduces leakage, achieving improved reliability through material parameter modification rather than structural complexity
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach results in GAA transistors with improved source/drain features, enhancing short-channel control, reducing sub-threshold leakage, and improving SRAM cell yield and operation margin.
Implementation Method 1
an adhesion layer within a source/drain region, which bonds to both Si channel layer surfaces and SiN inner spacer layer surfaces
Implementation Method 2
epitaxially growing a continuous first source/drain layer over the adhesion layer along the sidewall surface of the trench
Data Source
AI summary
A method of fabricating a device includes providing a fin extending from a substrate in a device type region, where the fin includes a plurality of semiconductor channel layers. In some embodiments, the method further includes forming a gate structure over the fin. Thereafter, in some examples, the method includes removing a portion of the plurality of semiconductor channel layers within a source/drain region adjacent to the gate structure to form a trench in the source/drain region. In some cases, the method further includes after forming the trench, depositing an adhesion layer within the source/drain region along a sidewall surface of the trench. In various embodiments, and after depositing the adhesion layer, the method further includes epitaxially growing a continuous first source/drain layer over the adhesion layer along the sidewall surface of the trench.