Thin Dummy Sidewall Spacers for Reduced-Pitch Transistors
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
In the formation of nano-structure transistors, the existing technologies face challenges in reducing the pitches of transistors while maintaining high growth selectivity for epitaxy regions, due to the thickness requirements of dummy sidewall spacers and hard masks.
Innovation Solution
The use of thin metal-containing hard masks and dummy sidewall spacers made from metal-containing materials like aluminum oxide, titanium oxide, and zirconium oxide, which provide improved growth selectivity even at reduced thicknesses, allowing for the reduction of transistor pitches.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Length of moving object
If conventional dummy sidewall spacers and hard masks are used, then growth selectivity is maintained, but transistor pitch cannot be reduced
Solution Approach 1:
The patent changes the material composition of the hard mask and dummy sidewall spacer from conventional materials to metal-containing materials (such as aluminum oxide, titanium oxide, zirconium oxide). This material parameter change enables these structures to maintain high growth selectivity even when their thickness is reduced to 5 nm or less, thereby allowing transistor pitch reduction while preserving epitaxial growth control
Solution Approach 2:
The patent employs composite material structures where metal-containing materials are combined with other semiconductor materials. The metal-containing hard mask and dummy sidewall spacer form a composite system that provides both the mechanical/structural function of spacing and masking, and the chemical function of providing high growth selectivity during epitaxial processes, enabling reduced dimensions without sacrificing performance
2Length of moving object
If the thickness of dummy sidewall spacers is reduced, then transistor pitch is reduced, but growth selectivity deteriorates
Solution Approach 1:
The patent fundamentally changes the material parameter of dummy sidewall spacers from conventional dielectric materials to metal-containing materials. This parameter change alters the chemical properties of the spacer material, enabling it to provide high growth selectivity even at ultra-thin dimensions (5 nm or less), thus resolving the trade-off between thickness reduction and growth selectivity maintenance
Solution Approach 2:
The patent replaces the conventional mechanical/physical approach to achieving growth selectivity (relying on thick spacer layers to physically block epitaxial growth) with a chemical approach. The metal-containing materials provide inherent chemical resistance to epitaxial growth, allowing thin spacers to maintain selectivity through material chemistry rather than physical thickness
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables the reduction of transistor pitches while maintaining high growth selectivity, thereby improving the performance and efficiency of transistor formation processes.
Implementation Method 1
epitaxy regions are formed as the source/drain regions
Implementation Method 2
metal-containing hard masks and dummy sidewall spacers made from metal-containing materials like aluminum oxide, titanium oxide, and zirconium oxide, which provide improved growth selectivity even at reduced thicknesses
Data Source
AI summary
A method includes forming a first gate stack over a first semiconductor region, depositing a spacer layer on the first gate stack, and depositing a dummy spacer layer on the spacer layer. The dummy spacer layer includes a metal-containing material. An anisotropic etching process is performed on the dummy spacer layer and the spacer layer to form a gate spacer and a dummy sidewall spacer, respectively. The first semiconductor region is etched to form a recess extending into the first semiconductor region. The first semiconductor region is etched using the first gate stack, the gate spacer, and the dummy sidewall spacer as an etching mask. The method further includes epitaxially growing a source/drain region in the recess, and removing the dummy sidewall spacer after the source/drain region is grown.