Thin Dummy Sidewall Spacers for Reduced-Pitch Transistor Epitaxy
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Solution Overview
Problem
In the formation of nano-structure transistors, the existing technologies face challenges in achieving high growth selectivity for epitaxy regions, particularly when forming transistors of different conductivity types, which requires separate epitaxy processes and results in increased transistor pitches due to the thickness of dummy sidewall spacers.
Innovation Solution
The use of a thin metal-containing hard mask that also forms dummy sidewall spacers, allowing for improved growth selectivity even at reduced thicknesses. This enables the reduction of transistor pitches without compromising growth selectivity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional dummy sidewall spacers are formed to mask p-type transistor regions during n-type epitaxy, then growth selectivity is improved, but transistor pitch increases due to the thickness of the dummy spacers
Solution Approach 1:
The patent changes the material parameter of the dummy sidewall spacer from conventional materials (silicon oxide, silicon nitride) to metal-containing materials (tungsten, molybdenum, titanium nitride). This material parameter change enables the dummy spacer to provide equivalent or superior growth selectivity at a reduced thickness, thereby reducing transistor pitch while maintaining epitaxial growth control
Solution Approach 2:
The patent employs composite material structures where metal-containing layers are combined with dielectric materials to form the dummy sidewall spacer. This composite approach leverages the high growth selectivity of metal-containing materials while incorporating dielectric properties for process compatibility, achieving both reduced thickness and maintained functionality
2Productivity
If the thickness of dummy sidewall spacers is reduced to decrease transistor pitch, then transistor density is improved, but growth selectivity for epitaxy regions deteriorates
Solution Approach 1:
The patent fundamentally changes the material composition parameter of the dummy sidewall spacer to metal-containing materials, which possess inherently higher growth selectivity. This allows the spacer thickness to be reduced while maintaining sufficient epitaxial growth control, thereby increasing transistor density without sacrificing growth selectivity
3Reliability
If separate epitaxy processes are used for n-type and p-type nano-structure transistors, then material-specific performance is optimized, but manufacturing complexity increases
Solution Approach 1:
The patent creates a universal dummy sidewall spacer structure using metal-containing materials that can be applied to both n-type and p-type transistor fabrication. This multi-functional approach allows the same spacer design to serve different epitaxial processes, reducing the need for process-specific variations and simplifying overall manufacturing complexity while maintaining material-specific performance optimization
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The implementation of a thin metal-containing hard mask with dummy sidewall spacers achieves high growth selectivity, allowing for reduced transistor pitches and improved performance in nano-structure transistors.
Implementation Method 1
depositing a dummy spacer layer on the spacer layer, wherein the dummy spacer layer comprises a metal-containing material
Implementation Method 2
performing an anisotropic etching process on the dummy spacer layer and the spacer layer to form a gate spacer and a dummy sidewall spacer, respectively
Implementation Method 3
etching the first semiconductor region to form a recess extending into the first semiconductor region, wherein the etching the first semiconductor region is performed using the first gate stack, the gate spacer, and the dummy sidewall spacer as an etching mask
Implementation Method 4
epitaxially growing a source/drain region in the recess
Data Source
AI summary
A method includes forming a first gate stack over a first semiconductor region, depositing a spacer layer on the first gate stack, and depositing a dummy spacer layer on the spacer layer. The dummy spacer layer includes a metal-containing material. An anisotropic etching process is performed on the dummy spacer layer and the spacer layer to form a gate spacer and a dummy sidewall spacer, respectively. The first semiconductor region is etched to form a recess extending into the first semiconductor region. The first semiconductor region is etched using the first gate stack, the gate spacer, and the dummy sidewall spacer as an etching mask. The method further includes epitaxially growing a source/drain region in the recess, and removing the dummy sidewall spacer after the source/drain region is grown.