Vertical DRAM Cell Structure With Air Gaps for Low-Parasitic Scaling
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Solution Overview
Problem
As the semiconductor industry continues to reduce minimum feature sizes to increase integration density, challenges arise in maintaining electrical characteristics and preventing unwanted memory characteristics in compact DRAM layouts.
Innovation Solution
The implementation of a vertical DRAM design with a gate-all-around transistor and integrated capacitor, allowing for a three-dimensional cell density by stacking memory cells and using a double layer of bit line wirings and air gaps to reduce parasitic capacitance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If minimum feature sizes are reduced to increase integration density, then more components can be integrated into a given area, but electrical characteristics deteriorate and unwanted memory characteristics arise
Solution Approach 1:
The patent transitions from planar 2D DRAM architecture to a 3D vertical architecture by stacking multiple memory cell layers vertically. This dimensional change allows continued scaling and increased integration density without further reducing lateral feature sizes, thereby maintaining electrical characteristics while achieving higher capacity.
Solution Approach 2:
The patent implements nested structures where word lines are wrapped around channel regions in a gate-all-around configuration, and multiple memory cell layers are stacked within a vertical column. This nesting enables compact 3D integration while maintaining proper electrical isolation and characteristics.
2Area of stationary object
If DRAM layout is made compact to reduce footprint, then area is reduced, but parasitic capacitance increases and electrical characteristics are compromised
Solution Approach 1:
By moving to a 3D vertical architecture, the patent reduces the lateral footprint while distributing capacitance effects across multiple vertical layers. The increased vertical separation between conductive elements in different layers reduces parasitic capacitance coupling compared to planar layouts.
Solution Approach 2:
The patent applies different dielectric materials with optimized properties in different regions and layers to locally manage and reduce parasitic capacitance. Air gaps and low-k dielectric regions are strategically placed between word lines and other conductive elements to minimize capacitive coupling.
3Quantity of substance
If vertical stacking is implemented to increase memory density, then integration capacity improves, but manufacturing complexity increases
Solution Approach 1:
The patent divides the manufacturing process into discrete, repeatable stages for forming each memory cell layer, including separate steps for depositing channel regions, gate dielectrics, word lines, and bit lines. This segmentation allows systematic control and optimization of each layer while maintaining overall process manageability.
Solution Approach 2:
The patent employs universal deposition and patterning processes that can be repeated for each layer, with materials and techniques serving multiple functions across different layers. This multi-functionality reduces the need for specialized processes for each layer, managing manufacturing complexity.
Data Source
AI summary
Embodiments provide an integrated capacitor disposed directly over and aligned to a vertical gate all around memory cell transistor. In some embodiments, an air gap may be provided between adjacent word lines to provide a low k dielectric effect between word lines. In some embodiments, a bottom bitline structure may be split across multiple layers. In some embodiments, a second tier of vertical cells may be positioned over a first tier of vertical cells.