Backside Power Rail Formation with PAI for Leakage-Free Contacts
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Solution Overview
Problem
As semiconductor devices shrink, forming backside power rails becomes challenging due to reduced process windows and increased parasitic capacitance, with conventional dry etching causing damage to dummy plugs and wet etching leaving residual silicon that introduces leakage paths.
Innovation Solution
A method involving the formation of a fin-shape structure, recessing source and drain regions, extending the source opening, forming a semiconductor plug, and then using a pre-amorphous implantation process followed by wet etching to uniformly remove the semiconductor layer, allowing for the formation of a backside power rail without damaging gate structures or introducing leakage paths.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If conventional dry etching is used to remove the semiconductor layer, then the etching process is fast and efficient, but the dummy plugs are damaged and leakage paths are introduced
Solution Approach 1:
A pre-amorphous implantation process is performed before wet etching to convert the crystalline semiconductor layer into an amorphous state. This preliminary action enables selective removal of the semiconductor layer while preserving the dummy plugs, as the amorphous structure etches at a different rate than the crystalline dummy plug material.
Solution Approach 2:
The patent changes the physical state of the semiconductor layer from crystalline to amorphous through ion implantation. This parameter change creates a distinct etching characteristic that allows selective removal of the semiconductor layer using wet etching without affecting the dummy plugs, thereby eliminating leakage paths while maintaining manufacturing efficiency.
2Reliability
If conventional wet etching is used to remove the semiconductor layer, then the process is gentle and selective, but residual silicon remains that introduces leakage paths
Solution Approach 1:
The pre-amorphous implantation process is performed as a preliminary step before wet etching. This conversion of the semiconductor layer to an amorphous state enables complete removal without residuals, as amorphous silicon etches uniformly and completely with wet etchants, eliminating the leakage paths that would otherwise remain after conventional wet etching of crystalline silicon.
3Reliability
If the semiconductor layer is completely removed to eliminate leakage paths, then reliability improves, but gate structures may be damaged
Solution Approach 1:
The patent applies local quality by creating different material states in different regions. The pre-amorphous implantation selectively amorphizes the semiconductor layer while leaving the gate structures intact. The subsequent wet etching then selectively removes only the amorphous semiconductor layer, achieving complete removal without damaging the gate structures due to their different material composition and structure.
Solution Approach 2:
The semiconductor layer is treated as a disposable sacrificial layer that is completely removed after serving its purpose. The pre-amorphous implantation enables this complete removal without residuals, and the selective nature of the process ensures that permanent structures like gate structures are not damaged in the process.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This method effectively reduces parasitic capacitance and eliminates leakage paths, improving the reliability and performance of semiconductor devices by allowing for efficient formation of backside power rails.
Implementation Method 1
performing a pre-amorphous implantation (PAI) process to amorphize the substrate
Implementation Method 2
replacing the amorphized substrate with a dielectric layer
Data Source
AI summary
A semiconductor structure and a method of forming the same are provided. An exemplary method of forming the semiconductor structure includes forming a semiconductor sacrificial plug in a substrate, forming a transistor over the substrate and on the semiconductor sacrificial plug, performing a pre-amorphous implantation (PAI) process from a back side of the substrate to amorphize at least a portion of the substrate, replacing the substrate with a dielectric layer, and replacing the semiconductor sacrificial plug with a backside contact. The semiconductor sacrificial plug and the substrate have different compositions. The transistor includes a source region and a drain region, a channel region disposed between the source region and the drain region, and a gate structure disposed over the channel region.