Hybrid-Fin Gate Structure for Easier Dummy Gate Replacement

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Solution Overview

Problem

As the minimum feature sizes in semiconductor devices are reduced, challenges arise in maintaining the integration density and processing window for operations such as the replacement gate process and epitaxial growth.

Innovation Solution

Forming dummy gates with a small footing profile around semiconductor fins and nanostructures, which are surrounded by a hybrid fin, increases the processing window for subsequent operations.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If minimum feature sizes are reduced to improve integration density, then more components can be integrated into a given area, but processing window for subsequent operations deteriorates

Engineering Contradiction:
Improveintegration densityVSAvoidprocessing window
Core Design Contradiction:
ProductivityVSManufacturing precision

Solution Approach 1:

The gate structure is segmented into multiple functional regions: a first gate portion with a first footprint profile and a second gate portion with a second footprint profile. This segmentation allows each portion to be optimized independently for its specific function, enabling the overall structure to achieve both high integration density and adequate processing window for subsequent operations.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

Different portions of the gate structure are assigned different footprint profiles tailored to their local requirements. The first gate portion has a footprint optimized for its function, while the second gate portion has a different footprint optimized for subsequent processing operations. This local optimization resolves the contradiction between integration density and processing window.

Inventive Principle:
Principle #3Local quality

2Reliability

If dummy gates are formed with conventional profiles, then gate functionality is achieved, but removal of dummy gates becomes difficult and may damage epitaxial source/drain regions

Engineering Contradiction:
Improvegate functionalityVSAvoiddummy gate removal
Core Design Contradiction:
ReliabilityVSEase of manufacture

Solution Approach 1:

The dummy gate structure incorporates a specific footprint profile that creates local geometric characteristics facilitating selective removal. The first and second gate portions have different footprint profiles, with the second portion designed to be more easily removable while maintaining gate functionality during operation. This local quality differentiation enables easy dummy gate removal without damaging epitaxial source/drain regions.

Inventive Principle:
Principle #3Local quality

Solution Approach 2:

The dummy gate structure is designed with predetermined geometric features (specific footprint profiles) that prepare it for future removal operations. The structure is configured in advance to allow selective removal of the second gate portion while preserving the first gate portion and underlying epitaxial source/drain regions, making the removal process straightforward and safe.

Inventive Principle:
Principle #10Preliminary action

3Ease of manufacture

If conventional gate structures are used, then manufacturing is simplified, but voids form in replacement gates reducing device performance

Engineering Contradiction:
Improvemanufacturing simplicityVSAvoiddevice performance
Core Design Contradiction:
Ease of manufactureVSReliability

Solution Approach 1:

The gate structure employs different footprint profiles for different portions to prevent void formation. The specific geometric configuration of the first and second gate portions ensures proper material distribution and contact during the replacement gate process, eliminating voids that would otherwise form and degrade device performance while maintaining manufacturing feasibility.

Inventive Principle:
Principle #3Local quality

Data Source

PatentUS12324191B2Transistor gate structures and methods of forming the same
Publication Date: 2025.06.03 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD
  • US12324191B2 patent drawing
  • US12324191B2 patent drawing
  • US12324191B2 patent drawing

AI summary

In an embodiment, a device includes: an isolation region; nanostructures protruding above a top surface of the isolation region; a gate structure wrapped around the nanostructures, the gate structure having a bottom surface contacting the isolation region, the bottom surface of the gate structure extending away from the nanostructures a first distance, the gate structure having a sidewall disposed a second distance from the nanostructures, the first distance less than or equal to the second distance; and a hybrid fin on the sidewall of the gate structure.