Stacked GAA FET Bottom Contact for Self-Aligned Current Control
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Solution Overview
Problem
As fin width in finFETs approaches 5 nm, channel width variations lead to undesirable variability and mobility loss, which gate-all-around (GAA) FETs aim to mitigate by placing a gate on all four sides of the channel.
Innovation Solution
The method involves forming a stacked gate-all-around field effect transistor (GAA FET) by creating a nanosheet stack over a substrate, forming fins and spacers, and then forming n-type and p-type epitaxial regions. A first contact is formed extending vertically through the GAA FET to directly contact the sidewall of an n-type epitaxial region.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Length of moving object
If fin width in finFET is reduced to approach 5 nm, then device scaling is achieved, but channel width variations cause undesirable variability and mobility loss
Solution Approach 1:
The patent transitions from 2D planar FET to 3D gate-all-around FET structure, where the gate wraps around the channel in all directions. This dimensional change provides uniform gate control over the channel from all sides, eliminating the variability issues associated with reduced fin width in conventional finFETs.
Solution Approach 2:
The patent employs composite material structures including alternating layers of different semiconductor materials (e.g., Si/SiGe) in the nanosheet stack, with various spacer materials and gate materials. This composite approach enables precise control of channel properties while maintaining uniform dimensions.
2Reliability
If gate-all-around structure is implemented, then control over current flow is improved, but device complexity increases
Solution Approach 1:
The gate structure is segmented into multiple gates stacked vertically, each wrapping around the channel. This segmentation allows independent control of different channel regions and simplifies the fabrication process by breaking down the complex 3D gate formation into manageable steps.
Solution Approach 2:
The gate structure implements a nested configuration where multiple gate layers are stacked around the central channel, similar to nested dolls. This nested arrangement provides complete surround control while maintaining a compact structure that fits within the device footprint.
3Manufacturing precision
If self-aligned bottom contact is formed, then manufacturing precision is improved, but process steps increase
Solution Approach 1:
The bottom contact region is prepared in advance during the nanosheet stack formation and spacer deposition steps. The contact opening is defined early in the process through self-alignment with the nanosheet edges, eliminating the need for subsequent alignment steps and improving manufacturing precision.
Solution Approach 2:
The structure itself provides the alignment references for contact formation. The nanosheet edges and spacer structures automatically define the contact opening position, making the alignment process self-directed without requiring additional lithography or etching steps.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables the formation of a self-aligned bottom contact for GAA FETs, improving control over current flow and reducing variability, thus enhancing the transistor's performance and mobility.
Implementation Method 1
forming n-type epitaxial regions between the plurality of fins, forming p-type epitaxy regions over the n-type epitaxial regions
Data Source
AI summary
A method is presented for constructing a semiconductor device. The method includes forming a plurality of fins over a nanosheet stack and a substrate, forming spacers between the nanosheet stack and one or more of the plurality of fins, each spacer defining a different shape, forming gate spacers adjacent the plurality of fins, the gate spacers directly contacting the one or more of the plurality of fins having a spacer, forming a barrier spacer between a set of fins of the plurality of fins, the barrier spacer directly contacting a top surface of a shallow trench isolation (STI) region, forming n-type epitaxial regions between the plurality of fins, forming p-type epitaxy regions over the n-type epitaxial regions, and forming a first contact extending vertically through the semiconductor device adjacent the barrier spacer and extending laterally away from the barrier spacer to directly contact a sidewall of an n-type epitaxial region.