Multi-Gate GAA FET Seed Layer Layout for Defect-Free Epitaxy
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Solution Overview
Problem
The integration of gate-all-around field effect transistor (GAA FET) devices with stacked nanosheets poses challenges, particularly in forming inner spacer layers that can lead to voids or defects during source/drain epitaxial growth due to limited semiconductor seed area.
Innovation Solution
A method for fabricating GAA FET devices involves forming a semiconductor seed layer on an inner spacer layer, which facilitates the subsequent formation of source/drain epitaxial features by providing a larger semiconductor surface area in the source/drain trench.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If an inner spacer layer is formed in the source/drain trench, then isolation between source/drain regions and gate stack is improved, but semiconductor seed area is reduced leading to voids or defects during epitaxial growth
Solution Approach 1:
The source/drain trench is segmented into multiple regions: the inner spacer layer occupies the central portion providing isolation, while semiconductor seed layers are deposited on the sidewalls providing epitaxial growth sites. This segmentation allows both isolation and sufficient seed area to coexist.
Solution Approach 2:
The semiconductor seed layers are positioned on the sidewalls (vertical dimension) rather than only on the bottom surface (horizontal dimension). This dimensional transition increases the available seed area without compromising the horizontal isolation provided by the inner spacer layer.
2Reliability
If the inner spacer layer completely fills the source/drain trench, then isolation is maximized, but no semiconductor seed area is available for epitaxial growth
Solution Approach 1:
The inner spacer layer provides high-quality isolation in the central region of the trench, while the sidewall regions are dedicated to semiconductor seed layer deposition. Each region has optimized local quality for its specific function: isolation versus epitaxial growth.
3Adaptability or versatility
If conventional CMOS processes are used for GAA FET fabrication, then compatibility is maintained, but integration of GAA features around stacked nanosheets becomes challenging
Solution Approach 1:
The inner spacer layer and semiconductor seed layers are formed preliminarily before the epitaxial growth of source/drain features. This preliminary action prepares the structure in advance, making the subsequent epitaxial growth step straightforward and compatible with conventional CMOS process flows.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach improves the quality of source/drain epitaxial features by reducing defects and enhancing the isolation between source/drain regions and the gate stack, while being easily integratable into existing semiconductor fabrication processes.
Implementation Method 1
growing a source/drain epitaxial layer in the source/drain trench, wherein the growing of the source/drain epitaxial layer includes growing the source/drain epitaxial layer from the seeding layer
Data Source
AI summary
The present disclosure provides a semiconductor device that includes channel layers vertically stacked over a substrate, a gate structure engaging the channel layers, a source/drain (S/D) formation assistance region partially embedded in the substrate and under a bottommost one of the channel layers, and an S/D epitaxial feature interfacing both the S/D formation assistance region and lateral ends of the channel layers. The S/D formation assistance region includes a semiconductor seed layer embedded in an isolation layer. The isolation layer separates the semiconductor seed layer from physically contacting the substrate.