Self-Aligned Inner Spacer for Smooth GAA Source/Drain Epitaxy

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Solution Overview

Problem

The fabrication of gate-all-around (GAA) transistors faces challenges due to poor epitaxial source and drain (S/D) growth, which results in mobility reduction and performance degradation.

Innovation Solution

The formation of self-aligned inner spacers by reflowing semiconductor layers provides a smooth S/D region interface, improving epitaxial S/D feature growth and reducing interface defects.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If conventional fabrication processes are used for GAA transistors, then gate control is improved through multi-gate structure, but epitaxial source and drain growth quality deteriorates due to surface roughness

Engineering Contradiction:
Improvegate controlVSAvoidepitaxial S/D growth quality
Core Design Contradiction:
ReliabilityVSManufacturing precision

Solution Approach 1:

The method performs preliminary surface preparation by forming a sacrificial layer and performing selective etching to create a smooth template surface before epitaxial growth. This preliminary action ensures that the surface is properly prepared in advance, preventing the surface roughness that would otherwise degrade epitaxial S/D growth quality while maintaining the GAA structure's gate control benefits

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The patent introduces a sacrificial layer as an intermediary element between the substrate and the epitaxial S/D regions. This sacrificial layer serves as a temporary structure that enables controlled surface preparation and provides a smooth interface for subsequent epitaxial growth, resolving the contradiction between maintaining gate control and achieving high-quality S/D growth

Inventive Principle:
Principle #24Intermediary (Mediator)

2Ease of manufacture

If epitaxial S/D features are grown on rough surfaces, then fabrication process is simplified, but device performance deteriorates due to mobility reduction

Engineering Contradiction:
Improvefabrication process simplicityVSAvoiddevice performance
Core Design Contradiction:
Ease of manufactureVSReliability

Solution Approach 1:

The method performs preliminary surface conditioning through controlled etching of the sacrificial layer to create a smooth surface template before epitaxial growth. This preliminary surface preparation enables high-quality epitaxial S/D growth without complicating the overall fabrication process, thereby maintaining ease of manufacture while improving device performance through reduced surface roughness

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The patent changes the surface morphology parameter by performing selective etching to transform the surface from rough to smooth. This parameter change in surface roughness directly improves carrier mobility and device performance while the etching process itself is integrated into the existing fabrication flow, maintaining ease of manufacture

Inventive Principle:
Principle #35Parameter changes

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

The smooth S/D region interface achieved by self-aligned inner spacers enhances epitaxial growth, reducing defects and improving the overall performance of GAA devices.

Implementation Method 1

performing a reflow process to the first semiconductor layer to form an inner spacer

Methodology Applied
Scientific EffectReflow: Annealing

Implementation Method 2

epitaxially growing a sour/drain feature in the source and drain region

Methodology Applied
Scientific EffectEpitaxial growth: Epitaxy

Data Source

PatentUS20250194203A1Self-aligned inner spacer on gate-all-around structure and methods of forming the same
Publication Date: 2025.06.12 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD
  • US20250194203A1 patent drawing
  • US20250194203A1 patent drawing
  • US20250194203A1 patent drawing

AI summary

Semiconductor device and the manufacturing method thereof are disclosed herein. An exemplary method of forming a semiconductor device comprises forming a fin over a substrate, wherein the fin comprises a first semiconductor layer and a second semiconductor layer comprising different semiconductor materials, and the fin includes a channel region and a source/drain region; forming a dummy gate structure over the substrate and the fin; etching a portion of the fin in the source/drain region; selectively removing an edge portion of the second semiconductor layer in the channel region of the fin such that the second semiconductor layer is recessed, and an edge portion of the first semiconductor layer is suspended; performing a reflow process to the first semiconductor layer to form an inner spacer, wherein the inner spacer forms sidewall surfaces of the source/drain region of the fin; and epitaxially growing a sour/drain feature in the source/drain region.