Stacked Channel MOSFET Structure for Scaled Device Reliability
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Solution Overview
Problem
The scaling down of MOSFETs in semiconductor devices leads to deterioration in operational properties, necessitating improvements in electrical characteristics and reliability.
Innovation Solution
A semiconductor device design featuring active patterns, source/drain patterns, gate electrodes, and channel patterns stacked on the active pattern, with specific configurations and insulating layers to enhance connectivity and reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of moving object
If MOSFETs are scaled down to meet increasing demand for smaller pattern size, then device size is reduced, but operational properties deteriorate
Solution Approach 1:
The patent transitions from planar channel structures to vertically stacked channel patterns, moving the channel conduction path into the third dimension. Multiple channel patterns are stacked vertically above the active pattern, enabling increased effective channel area without expanding the device footprint, thus maintaining operational properties while reducing device size.
Solution Approach 2:
The channel patterns are nested vertically within the device structure, with multiple channels stacked one above another. The gate electrode wraps around or positions adjacent to these stacked channels, creating a nested configuration where control structures surround the channel regions, maximizing space utilization and maintaining electrical performance in a compact form.
2Productivity
If channel patterns are stacked vertically to maintain connectivity, then device density increases, but manufacturing precision requirements increase
Solution Approach 1:
The gate electrode structure is formed first as a reference structure before depositing the channel patterns. This preliminary formation of the gate structure provides alignment references and positioning guides for subsequent channel pattern deposition, ensuring precise vertical stacking and registration of multiple channels without requiring extremely tight manufacturing tolerances.
Solution Approach 2:
Insulating patterns and spacer structures serve as intermediary elements between the gate electrode and channel patterns, and between adjacent channel patterns. These intermediary layers provide physical separation, electrical isolation, and mechanical support, facilitating the vertical stacking process and reducing the impact of manufacturing variations on final device performance.
Data Source
AI summary
A semiconductor device may include: an active pattern on a substrate and extending in a first direction; a plurality of source/drain patterns on the active pattern and spaced apart from each other in the first direction; a gate electrode between the plurality of source/drain patterns that crosses the active pattern and extends in a second direction intersecting the first direction; and a plurality of channel patterns stacked on the active pattern and configured to connect two or more of the source/drain patterns to each other. The channel patterns may be spaced apart from each other. Each of the channel patterns may include a first portion between the gate electrode and the source/drain patterns, and a plurality of second portions connected to the first portion and overlapped with the gate electrode in a direction perpendicular to a plane defined by an upper surface of the substrate.