Inter-Sheet Filler Layer for Multi-Patterned Metal Gate Threshold Control
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Solution Overview
Problem
Existing technologies face challenges in obtaining gate electrodes with desired characteristics for nanostructure transistors, particularly in achieving distinct threshold voltages and preventing erosion of gate dielectric materials during etching processes.
Innovation Solution
The formation of an inter-sheet filler layer between semiconductor nanostructures of different transistors, which is selectively removed to prevent the deposition of gate metals between certain nanostructures, thereby maintaining the integrity of gate dielectric materials and achieving distinct threshold voltages.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If gate metals are deposited between all semiconductor nanostructures to form gate electrodes, then the gate electrodes can be formed uniformly, but the gate dielectric materials between certain nanostructures will be eroded during etching processes and distinct threshold voltages cannot be achieved
Solution Approach 1:
The patent segments the gate electrode formation process by introducing an inter-sheet filler layer that selectively blocks gate metal deposition in specific regions. This allows different gate metal configurations for different transistor types (e.g., NFET vs PFET) on the same wafer, enabling distinct threshold voltages without eroding gate dielectric materials.
Solution Approach 2:
The inter-sheet filler layer acts as an intermediary element between the semiconductor nanostructures. It temporarily occupies spaces where gate metals should not be deposited, preventing direct contact between gate metals and gate dielectric materials in regions where distinct threshold voltages are required, thereby protecting the gate dielectric integrity.
2Adaptability or versatility
If multiple transistor types with distinct threshold voltages are fabricated on the same wafer, then computing power and device functionality are enhanced, but the process complexity increases and manufacturing difficulty arises
Solution Approach 1:
The inter-sheet filler layer is deposited beforehand to pre-determine which regions will receive gate metals and which will not. This preliminary action simplifies subsequent processing steps by eliminating the need for complex selective deposition or post-deposition removal procedures, thereby reducing overall fabrication complexity while enabling multiple transistor types.
Solution Approach 2:
The patent applies local quality by giving different regions of the wafer different gate metal configurations through the selective presence or absence of the inter-sheet filler layer. This allows NFETs and PFETs with distinct threshold voltages to coexist on the same wafer, enhancing adaptability without requiring entirely separate fabrication lines.
3Manufacturing precision
If etching processes are used to remove gate metals from between certain semiconductor nanostructures after deposition, then distinct threshold voltages can be achieved, but the gate dielectric materials are eroded and device reliability decreases
Solution Approach 1:
The inter-sheet filler layer provides preliminary anti-action by preemptively blocking gate metal deposition in regions where gate metals should not be present. This prevents the need for subsequent etching processes that would otherwise be required to remove gate metals, thereby avoiding erosion of gate dielectric materials and maintaining device reliability.
Solution Approach 2:
The patent converts the potential harm of gate metal deposition into a benefit by using the inter-sheet filler layer as a sacrificial placeholder. The filler layer is intentionally placed to block gate metal deposition, and its selective removal (without aggressive etching) achieves threshold voltage differentiation while preserving gate dielectric integrity.
Data Source
AI summary
An integrated circuit includes a first nanostructure transistor and a second nanostructure transistor. When forming the integrated circuit, an inter-sheet fill layer is deposited between semiconductor nanostructures of the second nanostructure transistor. A first gate metal layer is deposited between semiconductor nanostructures of the first nanostructure transistor while the inter-sheet filler layer is between the semiconductor nanostructures of the second nanostructure transistor. The inter-sheet filler layer is utilized to ensure that the first gate metal is not deposited between the semiconductor nanostructures of the second nanostructure transistor.