Fork-Sheet Semiconductor Layout for Wider Channels in Standard Cells
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Solution Overview
Problem
The challenge in the semiconductor industry is to maintain the trend of increasing semiconductor density while reducing power consumption and enhancing device speed, particularly in gate-all-around (GAA) devices like the Fork-Sheet (FS) structure, where the maximum device size is constrained by the standard cell height and minimum isolation space, making it difficult to accommodate wider devices within the same compact height.
Innovation Solution
The method involves partially removing the isolation-wall structure in standard cells to create a wider Fork-Sheet device across multiple cell heights, allowing the width of the FS device to increase by more than 1.5 times the original, achieved by altering the position of the isolation-wall within the unit cell, and merging N-type or P-type FS device regions to form an expanded device region with minimal isolation space between adjacent devices.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Length of moving object
If the standard cell height and minimum isolation space are maintained, then the device isolation and manufacturing precision are ensured, but the device width cannot be increased beyond the maximum device size constraint
Solution Approach 1:
The isolation wall is segmented into two separate isolation walls instead of one continuous isolation wall. This segmentation allows the channel pattern to be positioned between them, enabling the channel to extend across what would traditionally be a single isolation structure and effectively doubling the device width while maintaining proper isolation between adjacent devices
Solution Approach 2:
The patent transitions from a single-isolation-wall configuration to a multi-isolation-wall configuration, adding dimensional complexity to the isolation structure. By introducing multiple isolation walls at different positions, the device width can be increased without compromising the minimum isolation space requirements between adjacent devices
2Power
If the channel width is increased to improve drive current, then the device performance is enhanced, but the standard cell height constraint prevents accommodating wider devices
Solution Approach 1:
By segmenting the isolation structure into multiple walls, the patent enables the channel to span across multiple isolation sections, effectively increasing the channel width within the constrained cell height. This segmentation allows wider channels that can carry higher drive current without violating the standard cell height specification
Solution Approach 2:
The patent introduces flexibility in the isolation wall configuration, allowing the isolation structure to be dynamically adjusted from a single continuous wall to multiple separated walls. This dynamic reconfiguration enables the channel width to be optimized for high drive current while maintaining compatibility with standard cell height constraints
3Length of moving object
If the isolation wall is removed to create wider devices, then the device width increases by more than 1.5 times, but the isolation between adjacent devices may be compromised
Solution Approach 1:
The isolation wall is divided into multiple segments (first and second isolation walls) that are positioned to provide isolation between adjacent devices. This segmented approach allows the channel to be wider while ensuring that each isolation wall segment maintains the minimum isolation space requirement, thereby preserving device isolation reliability
Solution Approach 2:
The multiple isolation walls act as intermediary structures between adjacent devices, providing the necessary isolation while allowing the channel to extend wider. These intermediary isolation walls ensure that even as device width increases, the isolation between neighboring devices is maintained through the presence of these intermediate structures
Data Source
AI summary
A method includes forming first, second, third, fourth, fifth, and sixth channel patterns on a semiconductor substrate; forming a first isolation wall interposing the first and second channel patterns, a second isolation wall interposing the third and fourth channel patterns, wherein the first isolation wall further continuously extends to interpose the fifth and sixth channel patterns; forming a first gate pattern extending across the first, second, third, and fourth channel patterns and the first and second isolation walls, and a second gate pattern extending across the fifth and sixth channel patterns and the first isolation wall from the top view, wherein the first, second, third, fourth, and sixth channel patterns respectively have first, second, third, fourth, and sixth dimensions in a lengthwise direction of the first gate pattern, and the sixth dimension is greater than the first, second, third, and fourth dimensions.