Forksheet Transistor Gate Grid and Contact Cut for Tight Lithography
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Solution Overview
Problem
The scaling of multi-gate and nanowire transistors in integrated circuits faces challenges in maintaining mobility improvement and short channel control, particularly due to constraints on lithographic processes and spacing between features, which affect device performance and fabrication complexity.
Innovation Solution
The implementation of a uniform grid metal gate and trench contact cut in a forksheet transistor architecture, utilizing a 'plug-last' approach where gate dielectric layers are formed after metal gate deposition, allowing for seamless work function metal deposition and reducing space constraints, thereby improving device performance and reducing process variation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Length of moving object
If conventional multi-gate transistor fabrication processes are used, then device dimensions can be scaled down, but lithographic process constraints and spacing between features worsen, affecting device performance
Solution Approach 1:
The patent transitions from planar transistor architectures to three-dimensional forksheet and nanowire structures. By stacking multiple semiconductor layers vertically and creating multi-gate configurations, the invention achieves continued scaling of effective channel width without proportionally reducing lithographic feature sizes, thereby maintaining manufacturing precision while improving device dimensions
Solution Approach 2:
The forksheet architecture nests multiple semiconductor layers within a compact vertical structure, with each layer contributing to the effective channel width. This nested configuration allows the transistor to achieve higher drive current and improved performance without requiring proportional increases in lateral spacing, thus resolving the lithographic constraint issue
2Quantity of substance
If feature size is reduced to increase device density, then capacity increases, but spacing between features decreases, creating lithographic constraints
Solution Approach 1:
By moving from two-dimensional planar transistors to three-dimensional stacked architectures, the invention increases device density by utilizing the vertical dimension. Multiple active channels are stacked vertically, achieving higher quantity of functional units without proportionally reducing the lateral spacing between features, thus easing lithographic process constraints
Solution Approach 2:
The transistor channel is segmented into multiple discrete semiconductor layers stacked vertically, with each layer forming an independent conduction path. This segmentation allows the total effective channel width to be increased through stacking rather than lateral expansion, thereby increasing device density while maintaining adequate spacing between features for lithographic fabrication
3Area of stationary object
If uniform grid metal gate and trench contact cut architecture is implemented, then space constraints are alleviated and metal fill is facilitated, but fabrication process complexity increases
Solution Approach 1:
The uniform grid architecture employs a single patterning process that simultaneously defines both the metal gate locations and the trench contact positions. This multi-functional approach uses one lithographic step to create multiple critical features, thereby alleviating space constraints and reducing the number of fabrication steps despite the sophisticated final structure
Data Source
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AI summary
Integrated circuit structures having uniform grid metal gate and trench contact cut in a forksheet transistor architecture are described. In an example, a structure includes a dielectric backbone. First and second vertical stacks of nanowires are laterally adjacent to and in contact with first and second sides, respectively, of the dielectric backbone. First and second gate electrodes are around the first and second vertical stacks of nanowires, respectively, and are in contact with the first and second sides of the dielectric backbone, respectively. A first dielectric cut plug structure is adjacent to and in contact with the first gate electrode. A second dielectric cut plug structure is adjacent to and in contact with the second gate electrode. The second dielectric cut plug structure is parallel with the first dielectric cut plug structure.