Forksheet Semiconductor Structure With Stepped Isolation Gates
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Solution Overview
Problem
The performance of existing fork nanosheet (forksheet) semiconductor structures needs improvement, particularly in scalability and electrical isolation, as the accuracy requirements of photolithography processes become challenging with shrinking sizes, leading to potential connectivity issues between gate structures.
Innovation Solution
A semiconductor structure with a substrate having first and second regions, featuring isolation structures and nanostructures with specific gate structures that expose or contact on top surfaces, allowing for electrical isolation and connection, thereby simplifying the production process and improving performance by enabling separate formation of devices on the same substrate.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If a dielectric wall is introduced between NMOS and PMOS devices to reduce spacing, then scalability and area utilization are improved, but electrical isolation between gate structures becomes challenging and connectivity issues may arise
Solution Approach 1:
The patent divides the gate structure formation into two independent segments: NMOS gate structures are formed first and exposed on the first isolation structure, then PMOS gate structures are formed separately and contact the second isolation structure. This segmentation allows each gate to be independently formed and isolated, preventing connectivity issues while maintaining scalability.
Solution Approach 2:
The patent introduces a vertical dimension solution by using two different isolation structures at different heights. The first isolation structure exposes its top surface for NMOS gate contact, while the second isolation structure is lower and contacted by PMOS gates from above. This vertical differentiation ensures electrical isolation between NMOS and PMOS gates while allowing dense lateral packing for scalability.
2Manufacturing precision
If photolithography accuracy is maintained with shrinking device sizes, then manufacturing precision is improved, but process complexity and difficulty increase significantly
Solution Approach 1:
The patent segments the gate formation process into two independent stages: first forming NMOS gates with their isolation structure, then forming PMOS gates with their separate isolation structure. This segmentation simplifies each individual lithography step compared to forming all gates simultaneously, reducing process complexity while maintaining precision requirements.
Solution Approach 2:
The patent performs preliminary actions by first forming the first isolation structure and NMOS gate structures before forming the second isolation structure and PMOS gate structures. This preliminary formation allows each gate type to be optimized independently and simplifies subsequent processing steps, reducing overall process complexity.
3Reliability
If gate structures are formed to ensure electrical isolation, then reliability is improved, but production process complexity increases
Solution Approach 1:
The patent segments the isolation and gate formation into two independent processes: first isolation structure with NMOS gates, then second isolation structure with PMOS gates. This segmentation achieves reliable electrical isolation between device types while keeping each process module simple and manageable.
Solution Approach 2:
The patent introduces isolation structures as intermediary elements between NMOS and PMOS device regions. The first isolation structure mediates NMOS gate formation and exposure, while the second isolation structure mediates PMOS gate formation and contact, ensuring electrical isolation without requiring complex direct isolation mechanisms between gates.
Data Source
AI summary
Semiconductor structure and method of forming semiconductor structure are provided. The semiconductor structure includes a substrate, a first isolation structure, and a first nanostructure and a second nanostructure on two sides of the first isolation structure. The semiconductor structure also includes a second isolation structure, and a third nanostructure and a fourth nanostructure on two sides of the second isolation structure. A top of the second isolation structure is lower than a top of the first isolation structure. The semiconductor structure also includes a first gate structure and a second gate structure. The first gate structure and the second gate structure expose a top surface of the first isolation structure. The semiconductor structure also includes a third gate structure and a fourth gate structure. The third gate structure and the fourth gate structure are in contact with each other on a top surface of the second isolation structure.