Formal Generated-Clock Timing Verification
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Solution Overview
Problem
Current integrated circuit design tools, such as Atrenta's Spyglass Clk_Gen23, are limited in verifying clock timing definitions due to their structural checking methods, which cannot handle complex logic structures and may miss errors in generated-clock definitions, leading to potential chip functionality issues if mistakes are made in clock timing information.
Innovation Solution
A generated-clock checker software tool using formal methods compares user-specified timing definitions against a register transfer level design, deriving and comparing waveform models to identify discrepancies, and reports mismatches or missing definitions, allowing for user visualization and correction of timing errors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If structural checking methods are used to verify clock timing definitions, then the verification process is simple and fast, but the method cannot handle complex logic structures and may miss errors in generated-clock definitions
Solution Approach 1:
The patent replaces structural checking methods with formal methods based on mathematical logic and theorem proving. The system uses formal verification techniques to rigorously verify clock timing definitions against the register transfer level design, transforming the verification process from heuristic structural analysis to mathematically rigorous proof-based verification. This substitution enables complete coverage of complex logic structures while maintaining verification accuracy.
2Reliability
If formal methods are used to verify clock timing definitions, then verification accuracy and completeness are improved, but the verification process becomes more complex and computationally intensive
Solution Approach 1:
The patent performs preliminary actions by extracting and analyzing clock timing definitions from the register transfer level design before formal verification. The system identifies all clock signals, their relationships, and timing parameters in advance, preparing the verification data structure that will be used in the formal verification process. This preliminary extraction reduces the computational burden during actual verification by pre-organizing the data in a verification-friendly format.
Solution Approach 2:
The patent changes the verification parameters from structural characteristics to temporal and logical properties. By transforming the verification focus from structural correctness to timing parameter accuracy (period, phase, frequency relationships), the system enables more efficient formal verification. The parameter transformation allows the use of temporal logic and mathematical modeling to verify timing definitions, which is more computationally efficient than exhaustive structural analysis of complex logic networks.
3Reliability
If comprehensive logic path analysis is performed to verify all generated clocks, then verification completeness is improved, but the analysis complexity and resource requirements increase significantly
Solution Approach 1:
The patent extracts only the essential information needed for verification from the complex register transfer level design. By extracting clock timing definitions, register transitions, and timing parameters while filtering out irrelevant structural details, the system reduces the verification problem to a manageable set of critical timing relationships. This extraction approach maintains verification completeness for all generated clocks while significantly reducing the complexity of analysis required.
Solution Approach 2:
The patent segments the verification process into distinct modules: clock signal identification, timing parameter extraction, logic path analysis, and formal verification. Each module handles a specific aspect of verification independently, allowing the system to manage complexity through modular processing. The segmentation enables systematic verification of all generated clocks while maintaining computational efficiency through localized analysis of specific timing paths.
Data Source
AI summary
A generated-clock checker compares timing definitions against a register transfer level description of the design using formal methods. The generated-clock checker derives generated-clock timing waveform models from the timing definitions, derives generated-clock waveform models from the register level design and then compares the waveform models using formal methods.