Forward-Biased Synchronizer Circuit for Lower Metastability Tau
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Solution Overview
Problem
Conventional synchronizers face challenges in minimizing the metastability resolving timing constant (Tau) without increasing the number of stages or altering system requirements, leading to inefficiencies in metastability control and increased power and area consumption, especially in systems-on-chip (SoC) with multiple asynchronous domains.
Innovation Solution
The implementation of NWell and PWell forward biasing techniques, along with mixed voltage threshold technologies, optimizes flip-flop circuitry to reduce Tau values, allowing for controlled metastability management with only two flip-flops, while minimizing area and power penalties.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional synchronizer designs are used, then the basic synchronization function is provided, but the metastability resolving timing constant (Tau) cannot be minimized without increasing the number of stages
Solution Approach 1:
The patent applies parameter changes by modifying the voltage threshold characteristics of transistors within the flip-flop circuit. Specifically, it uses mixed voltage threshold technologies (combining low-voltage-threshold and high-voltage-threshold transistors) and adjusts bias voltages to optimize the metastability resolving timing constant Tau. This allows achieving better metastability control with only two stages instead of requiring more stages as in conventional designs.
2Reliability
If the number of flip-flops is increased to reduce Tau, then metastability control improves, but area and power consumption increase
Solution Approach 1:
The patent achieves better MTBF with reduced area by changing the electrical parameters of the existing two-stage synchronizer. It employs mixed voltage threshold transistors and optimized biasing schemes to reduce the metastability resolving timing constant Tau, thereby improving MTBF without adding more flip-flops or increasing the synchronizer area.
3Device complexity
If conventional flip-flop circuitry is used, then the circuit structure remains simple, but leakage current and area penalties increase
Solution Approach 1:
The patent applies local quality by selectively using different voltage threshold transistors in different parts of the flip-flop circuit. It combines low-voltage-threshold transistors (for faster switching and lower leakage in critical paths) with high-voltage-threshold transistors (for reduced leakage in non-critical paths), optimizing the overall circuit performance while maintaining structural simplicity.
4Reliability
If more stages are added to the synchronizer, then metastability control improves, but power consumption increases
Solution Approach 1:
The patent reduces power consumption while maintaining metastability control by changing the voltage threshold parameters and bias conditions of the two-stage synchronizer. The mixed voltage threshold approach and optimized biasing enable the circuit to achieve lower Tau values with reduced dynamic and static power dissipation compared to conventional uniform-voltage-threshold multi-stage synchronizers.
Data Source
Figure 1~2A
Figure 2B~2C
Figure 3
AI summary
Synchronizer circuits having controllable metastability are provided, one of which includes: a first flip-flop circuit comprising a first master latch connected in series with a first slave latch; and a second flip-flop circuit comprising a second master latch connected in series with a second slave latch, wherein an output of the first flip-flop circuit is connected to an input of the second flip-flop circuit, at least a portion of the first flip-flop circuit is implemented in a first PWell isolated by an underlying a deep isolation NWell, at least a portion of the first flip-flop circuit is implemented in a first NWell that electrically contacts the deep isolation NWell, the first NWell is connected to a first bias voltage that is less than a positive power supply voltage, and the first PWell is connected to a second bias voltage that is greater than a negative power supply voltage.