Semiconductor DFT Interfaces with Forwarded-Clock Test Lanes
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Solution Overview
Problem
The existing testing methods for integrated circuit devices face challenges due to the limitations of the Joint Action Test Group (JTAG) Institute of Electrical and Electronics Engineers (IEEE 1149.1) standard, which has a narrow pin count and low data rate, leading to high test cost, complexity, and reduced bandwidth, making it difficult to scale up with increasing transistor counts and performance demands.
Innovation Solution
A design for test (DFT) interface that utilizes a forwarded clock architecture with adjustable RX and TX lanes, supporting data rates from 2 bps to 2 Gbps, and employs automatic test equipment for resistance and timing calibration, eliminating the need for state machines and enabling flexible data rate operation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If JTAG IEEE 1149.1 standard is used for testing, then test access is provided, but pin count is narrow and data rate is low
Solution Approach 1:
The test interface is segmented into multiple parallel lanes (RX lanes and TX lanes) instead of using a single narrow JTAG interface. Each lane can operate independently at high data rates, allowing the total bandwidth to scale with the number of lanes while maintaining manageable pin counts through efficient multiplexing and serialization/deserialization logic.
Solution Approach 2:
The interface supports dynamic data rate adjustment from 2 bps to 2 Gbps based on testing requirements. The forwarded clock architecture allows the data rate to be changed without requiring physical reconfiguration, enabling the same hardware to adapt to different test scenarios and productivity requirements.
2Productivity
If JTAG standard is used, then test access is provided, but test cost becomes prohibitive at scale
Solution Approach 1:
Multiple high-speed lanes are merged through efficient serialization and deserialization logic that operates in parallel. The test network merges data from multiple RX lanes and combines them into a single test data stream, reducing the overall network complexity while maintaining high throughput capability.
Solution Approach 2:
The forwarded clock architecture enables continuous data transmission without interruption or waiting states. Once the interface is configured, data can be transmitted continuously at high rates without the start-stop overhead inherent in traditional JTAG sequences, improving test throughput and reducing test time.
3Productivity
If traditional test ports are used, then testing is enabled, but bandwidth fails to scale up
Solution Approach 1:
The interface transitions from a single-dimensional JTAG protocol to a multi-dimensional parallel lane architecture. By adding spatial dimension through multiple parallel RX and TX lanes, the bandwidth scales linearly with the number of lanes while each lane maintains manageable complexity through serialization/deserialization.
Solution Approach 2:
The interface supports parameter changes in data rate from 2 bps to 2 Gbps and in the number of active lanes based on testing requirements. This flexibility allows the same physical interface to adapt to different bandwidth requirements without requiring hardware changes, improving scalability and versatility.
4Reliability
If JTAG test ports are used, then testing is provided, but design performance is impacted
Solution Approach 1:
The test interface logic is extracted from the main device logic and placed in a dedicated test port architecture. This separation allows the test functionality to be isolated and optimized independently, improving test coverage without impacting the performance of the main device logic through reduced interference and dedicated test resources.
Data Source
AI summary
Semiconductor devices having design for test interfaces are provided. The semiconductor devices can be tested in a manufacturing environment as either a die or a packaged die. The design for test interface comprises a physical layer having transmitter, receiver, and a common lane. The design for test interface also comprises test port interface logic that can interface with the semiconductor device logic. Test port interface logic can include 1:N de-serializer logic, 1:N CLK divider logic, and N:1 serializer logic.