Four-Poly-Pitch SRAM Cell Layout With Backside Bit-Line Routing
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Solution Overview
Problem
Existing semiconductor technologies face challenges in reducing stray capacitance and resistance in SRAM cells, which affect performance and complexity in high-density integrated circuits.
Innovation Solution
A four-poly-pitch SRAM cell design with metal tracks on both the frontside and backside of a substrate, featuring FinFET and gate-all-around transistors, where bit lines and ground lines are placed on the backside to reduce coupling capacitance and resistance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If bit lines and ground lines are placed on the frontside of the substrate, then routing and connection are simplified, but coupling capacitance and resistance increase affecting performance
Solution Approach 1:
The patent moves bit lines and ground lines from the frontside to the backside of the substrate, utilizing the third dimension (depth/thickness) to resolve the contradiction. This spatial reconfiguration allows routing connections to remain simple while significantly reducing coupling capacitance between bit lines and transistor gates, as the backside placement increases physical separation between these conductive elements.
2Productivity
If feature size is scaled down to increase functional density, then production efficiency improves and costs decrease, but stray capacitance among features increases
Solution Approach 1:
By relocating bit lines to the backside of the substrate, the patent effectively uses vertical separation to reduce stray capacitance. This allows continued scaling of horizontal feature sizes while maintaining lower parasitic capacitance values, as the bit lines are now separated in the vertical dimension rather than competing for horizontal space.
Solution Approach 2:
The patent segments the interconnect structure into frontside components (word lines, select lines) and backside components (bit lines, ground lines). This segmentation allows each layer to be optimized independently, with the backside layer specifically designed to minimize coupling effects while the frontside layer maintains routing simplicity.
3Device complexity
If metal tracks are placed only on the frontside, then manufacturing process is simpler, but resistance and coupling capacitance are higher
Solution Approach 1:
The patent utilizes the backside of the substrate as an additional interconnect layer, effectively adding a dimensional degree of freedom to the interconnect architecture. This allows bit lines and ground lines to be routed on the backside, reducing their resistance by providing dedicated routing paths away from frontside congestion, and reducing coupling capacitance through increased physical separation from frontside transistor gates.
Data Source
AI summary
A semiconductor structure includes an SRAM cell that includes first and second pull-up (PU) transistors, first and second pull-down (PD) transistors, and first and second pass-gate (PG) transistors. A source, a drain, and a channel of the first PU transistor and a source, a drain, and a channel of the second PU transistor are collinear. A source, a drain, and a channel of the first PD transistor, a source, a drain, and a channel of the second PD transistor, a source, a drain, and a channel of the first PG transistor, and a source, a drain, and a channel of the second PG transistor are collinear.