Embedded ASIC Interconnect in FPGA for Faster Module Data Paths
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Solution Overview
Problem
Conventional FPGAs suffer from long delays and poor performance due to multi-stage cascading of routing resources, leading to low frequency operation and inefficient resource utilization, especially when dealing with large data bit widths and complex logic combinations.
Innovation Solution
Embedding ASIC-based hard cores with high-speed exchange and interconnection units and stations within the FPGA, allowing for direct proximity-based data transmission between functional modules and reducing routing delays by bypassing intermediate CLBs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If multi-stage cascading of routing resources is used for interconnection between functional modules, then routing flexibility is improved, but transmission delay increases and operating frequency decreases
Solution Approach 1:
The patent segments the interconnection system into two parts: a fast dedicated interconnect fabric for time-critical data transmission between functional modules, and the programmable routing resources for flexible but less time-critical communication. This segmentation allows simultaneous optimization of both speed and flexibility by using appropriate paths for different traffic types.
Solution Approach 2:
The patent introduces an intermediary high-speed interconnect fabric that mediates between functional modules requiring fast communication. This intermediary structure bypasses the multi-stage routing for time-critical paths while preserving routing flexibility for other communications, thus reducing transmission delay without sacrificing overall routing adaptability.
2Adaptability or versatility
If multi-stage cascading of routing resources is used for interconnection between functional modules, then routing flexibility is improved, but operating frequency decreases
Solution Approach 1:
The interconnection system is segmented into a high-speed dedicated interconnect fabric for frequency-critical operations and programmable routing for flexible but less frequency-sensitive communications. This allows the FPGA to achieve higher operating frequencies by providing deterministic low-latency paths for time-critical data flows.
Solution Approach 2:
A high-speed interconnect intermediary is introduced that provides deterministic timing characteristics for frequency-critical paths. This intermediary structure enables higher operating frequencies by ensuring that time-sensitive operations have guaranteed bandwidth and latency, while preserving routing flexibility for other operations.
3Speed
If ASIC-based hard cores with high-speed exchange units are embedded in FPGA, then data transmission speed is improved, but device complexity increases
Solution Approach 1:
The patent applies local quality by embedding ASIC-based hard cores with high-speed exchange units at specific strategic locations within the FPGA fabric where high-performance communication is required. This localized enhancement provides high-speed transmission only where needed, rather than making the entire device complex, thus achieving speed improvement with minimal impact on overall device complexity.
Data Source
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AI summary
The application provides a field programmable gate array FPGA and a communication method. At least one application specific integrated circuit ASIC-based hard core used for communication and interconnection is embedded in the FPGA. The ASIC-based hard core includes a high-speed exchange and interconnection unit and at least one station. Each station is connected to the high-speed exchange and interconnection unit. The station is configured to transmit data between each functional module in the FPGA and the ASIC-based hard core. The high-speed exchange and interconnection unit is configured to transmit data between the stations. In the FPGA provided by the application, an ASIC-based hard core is embedded, which can facilitate data exchange between each functional module and the ASIC-based hard core in proximity and reduce a time delay. A source functional module sends data to a station; the station sends the data to the high-speed exchange and interconnection unit; and the high-speed exchange and interconnection unit sends the data to a destination functional module by using a station connected to the destination functional module. In this way, data is transmitted between the source functional module and the destination functional module.