FPGA-Based ATE Test Board for DUT Simulation
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Solution Overview
Problem
Conventional automated test equipment (ATE) systems are limited by the processing capabilities of the tester processor, require protocol-specific hardware bus adapter cards, and are cumbersome and costly, making them inefficient for testing multiple devices under test (DUTs) with different communication protocols and unsuitable for development environments.
Innovation Solution
The system transfers command and test pattern generation functionality to FPGAs, allowing reconfigurable communication protocols and reducing the processing load on the tester processor, while using small-scale, programmable test boards that can simulate next-generation devices, enabling efficient testing of multiple DUTs with different protocols on a single hardware platform.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If conventional ATE systems use processor-based command and test pattern generation, then the system can be implemented with standard hardware, but the processing load on the tester processor becomes excessive and limits the number of DUTs that can be tested
Solution Approach 1:
The patent extracts the command and test pattern generation functionality from the tester processor and implements it using FPGA hardware accelerators. This separation allows the FPGA to handle the computationally intensive tasks independently, reducing the processing load on the tester processor and enabling simultaneous testing of multiple DUTs without overloading the processor.
Solution Approach 2:
The patent replaces the software-based command and test pattern generation mechanism with a hardware-based FPGA implementation. This substitution leverages the parallel processing capabilities of FPGA hardware to generate commands and test patterns much faster than software can, thereby increasing productivity while reducing the computational burden on the tester processor.
2Adaptability or versatility
If conventional ATE systems use protocol-specific hardware bus adapter cards, then communication with DUTs can be reliable, but the hardware becomes cumbersome and costly, and cannot be reconfigured for different protocols
Solution Approach 1:
The patent implements a universal FPGA-based interface that can be configured to support multiple communication protocols (PCIe, SATA, SAS, USB, etc.) through software programming rather than requiring separate hardware adapter cards for each protocol. This multi-functional approach allows a single hardware platform to adapt to different protocol requirements, eliminating the need for multiple specialized hardware components.
Solution Approach 2:
The patent employs dynamic reconfigurability where the FPGA can be reprogrammed to change its communication protocol capabilities. This dynamic adaptation allows the same physical hardware to serve different protocol needs by loading different bitstream configurations, providing versatility without requiring physical hardware changes or complex reconfiguration procedures.
3Ease of manufacture
If conventional ATE systems use dedicated tester processors and hardware components, then testing functionality can be comprehensive, but the system becomes large, expensive, and unsuitable for development environments
Solution Approach 1:
The patent creates a simplified copy of the testing functionality implemented through FPGA hardware accelerators that can be integrated into smaller, more affordable test systems. This approach allows the essential testing capabilities to be replicated in a compact form factor suitable for development environments, while the same FPGA-based architecture can scale up for production use, providing both cost-effectiveness and versatility.
Data Source
AI summary
An automated test equipment (ATE) system capable of performing a test of semiconductor devices is presented. The system comprises a first test board including a first FPGA communicatively coupled to a controller via an interface board, wherein the first FPGA comprises a first core programmed to implement a communication protocol, and further wherein the FPGA is programmed with at least one hardware accelerator circuit operable to internally generate commands and data for testing a DUT. The system also includes a second test board comprising a second FPGA communicatively coupled to the first test board, wherein the second FPGA comprises a second core programmed to implement a communication protocol for a device under test, wherein the second FPGA is further programmed to simulate a DUT, and wherein the first FPGA is operable to communicate with the second FPGA in order to test a communication link between the first test board and the second test board.