3D FPGA Chiplet Layout for Routing and Thermal Bottlenecks
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Solution Overview
Problem
Integrated circuit systems face challenges with routing congestion, bandwidth distribution, and thermal dissipation issues due to the placement of circuit components, which can lead to inefficiencies and increased development time for customized devices.
Innovation Solution
The approach involves disaggregating components of a monolithic integrated circuit into modular chiplets that can be arranged in 3D or side-by-side configurations, allowing for customizable and efficient integration of specific functionalities, such as programmable logic fabric, DSP, and memory, with optimized heat dissipation and communication through microbumps or hybrid bonds.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If circuit components are placed in shorelines of integrated circuits to enable communication between integrated circuits, then communication capability is improved, but routing congestion and bandwidth distribution issues occur within the main fabric die
Solution Approach 1:
The patent segments the integrated circuit into multiple independent die (compute die, memory die, I/O die) that can be separately designed and manufactured. Each die has dedicated interconnect resources, eliminating the routing congestion that occurs when all components share shoreline placement in monolithic designs. The segmentation allows each die to optimize its internal routing without interfering with other components.
Solution Approach 2:
The patent transitions from traditional 2D shoreline placement to 3D stacked architecture using through-silicon vias (TSVs) and microbumps. This dimensional change allows interconnect resources to be distributed vertically through multiple layers, providing abundant bandwidth without congesting any single plane. The interconnect resources extend in the vertical dimension rather than being constrained to shoreline perimeters.
2Ease of operation
If circuit components are placed in shorelines of integrated circuits to enable communication, then communication capability is improved, but thermal dissipation issues occur
Solution Approach 1:
The patent segments high-power components into separate die, allowing independent thermal management. Compute die, memory die, and I/O die can be stacked with thermal interface materials and heat sinks positioned between them, enabling heat to dissipate through multiple pathways rather than concentrating in a single shoreline region.
Solution Approach 2:
The 3D stacked architecture provides vertical thermal pathways through TSVs and thermal interface materials between die layers. Heat can escape through the top and bottom surfaces of the package rather than being trapped in the planar shoreline region, significantly improving thermal dissipation capability.
3Adaptability or versatility
If monolithic integrated circuit designs are created to meet various use case specifications, then versatility is improved, but development time and redundancy increase
Solution Approach 1:
The patent segments the integrated circuit into standardized, independently manufacturable die that can be mixed and matched to create customized systems. Pre-fabricated compute die, memory die, and I/O die with standardized interconnect interfaces can be combined in different configurations to meet diverse use case requirements without requiring new monolithic designs, dramatically reducing development time.
Solution Approach 2:
The patent creates universal interconnect interfaces and standardized die formats that can be used across multiple applications. The same compute die can be paired with different memory and I/O die configurations to serve various use cases, eliminating the need for redundant monolithic designs and reducing development time through component reuse.
Data Source
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AI summary
Systems and methods are provided for system circuitry disaggregation into an integrated circuit system (102c) with multiple chiplets (232c, 232f) having disaggregated components. A system may include a first programmable logic fabric die (232a) that includes programmable logic circuitry and a number of supporting chiplets (232c, 232f) that include disaggregated field programmable gate array, FPGA, circuitry. The chiplets are connected to the first programmable logic fabric die in a three-dimensional arrangement.