Adaptive Clock Phase Control in FPGA Data Communication
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Solution Overview
Problem
In the nanometer era, high-speed ASIC/SoC designs face challenges in increasing operating frequency due to limitations in programmable logic devices like FPGAs, where cycle-stealing techniques are not effective due to limited global clock lines and lack of sufficient timing information, leading to inefficiencies and potential system malfunction.
Innovation Solution
A programmable logic device with a multiplexer/de-multiplexer unit and a control unit that generates adaptively adjusted control signals to eliminate phase skew between clock signals, using a series of registers and logic gates to selectively provide control signals, allowing for improved clock signal management and reduced false signaling or glitches.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If cycle-stealing techniques are used to increase operating frequency, then operating frequency is improved, but the technique is not suitable for programmable logic devices due to limited global clock lines
Solution Approach 1:
The patent applies dynamics by making the clock signal phase adjustable and adaptive. The system dynamically shifts the phase of clock signals based on timing requirements of different logic paths, allowing the same clock line to serve multiple timing functions. This eliminates the need for multiple dedicated clock lines while maintaining the ability to meet different timing constraints.
Solution Approach 2:
The patent changes the parameter of clock signal phase to resolve the contradiction. By varying the phase of clock signals dynamically, the system can accommodate different timing requirements without adding more clock lines. The phase shift amount is adjusted based on the specific timing needs of logic elements, enabling frequency improvement within existing resource constraints.
2Speed
If skewed internal clock techniques are used, then operating frequency is increased, but hold violations occur with best case delays causing system malfunction
Solution Approach 1:
The patent implements feedback by continuously monitoring timing parameters and using this information to adjust clock signal phases. The system measures actual timing delays and dynamically adjusts phase shifts to prevent hold violations. This closed-loop approach ensures that frequency optimization does not compromise system reliability, as the phase adjustments are continuously adapted to maintain proper timing margins.
Solution Approach 2:
The patent applies preliminary action by pre-calculating and pre-adjusting clock phase shifts based on known timing characteristics of logic paths. Before signals are transmitted, the system prepares appropriate phase adjustments to ensure that timing constraints will be met. This proactive approach prevents hold violations before they occur, maintaining both high frequency operation and system reliability.
3Adaptability or versatility
If multi-FPGA partitioning is used, then complex ASIC/SoC can be emulated, but combinatorial paths between FPGAs become critical paths reducing operating frequency
Solution Approach 1:
The patent addresses this contradiction by adding a temporal dimension to clock signal distribution through dynamic phase shifting. Instead of treating clock distribution as a static spatial problem, the system introduces time-varying phase adjustments that compensate for combinatorial path delays. This allows multi-FPGA systems to maintain high operating frequencies despite the presence of inter-FPGA combinatorial paths, as each FPGA can receive clock signals with optimized phases for its specific timing requirements.
Data Source
AI summary
A programmable logic device is presented. The device comprises a plurality of logic elements and a plurality of I/O pins; a multiplexer and/or a de-multiplexer unit. The multiplexer and/or multiplexer unit is coupled between said logic elements and I/O pins. The device further comprises a control unit for generating control signal/s for selecting one of the inputs of the multiplexer and/or one of the outputs of the de-multiplexer. The control unit includes inputs for receiving a first clock signal, a second clock signal and indicators, said indicators being indicative of a phase skew relation amongst the clock signals. The control unit being configured for generating adaptively adjusted control signal/s according to the clock signals and indicators, said control signal/s are adaptively adjusted for eliminating impact of the phase skew amongst the clock signals.