Unified FPGA Debug Bridge for Soft and Hard Processors
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Debugging tools face challenges in providing a unified environment for debugging code executed on both soft processors implemented on FPGAs and hard processors on SoCs, as they often require separate debuggers and connections, limiting the ability to analyze and debug programs running on both types of processors effectively.
Innovation Solution
A unified debug environment is created by implementing a method and apparatus that includes a soft processor and hard processor debug unit on an FPGA, with a bus bridge to connect these units, allowing a single host debugger to access and debug both types of processors through a single port, and generating a debug unit identification file to identify available tools and their locations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If separate debuggers and connections are used for soft processors on FPGAs and hard processors on SoCs, then each processor type can be debugged with dedicated tools, but the debugging complexity increases and a unified debug environment cannot be achieved
Solution Approach 1:
The patent implements a unified debug environment where a single host debugger can debug both soft processors on FPGAs and hard processors on SoCs through a single connection interface. The debug bridge circuit enables one debugger to perform multiple debugging functions across different processor types, eliminating the need for separate dedicated debuggers for each processor type while maintaining full debugging capability for both.
Solution Approach 2:
The patent introduces a debug bridge circuit as an intermediary component that connects the host debugger to both soft processor debug units and hard processor debug units. This bridge acts as a mediator that translates and routes debug signals between different processor types and the single host debugger, enabling unified access while managing the complexity of interfacing with multiple processor architectures.
2Reliability
If multiple separate debug connections are implemented, then each processor can be accessed independently, but the number of connections and interfaces increases
Solution Approach 1:
The patent merges multiple separate debug connections into a single unified connection interface. The host debugger connects through one interface to the debug bridge, which then manages connections to both soft processor debug units and hard processor debug units. This combining of connections reduces the number of physical interfaces while maintaining reliable access to all processors through the bridge's routing capabilities.
3Productivity
If a unified debug environment is implemented with a single host debugger, then debugging complexity is reduced and efficiency is improved, but the requirements for the debug bridge and tool compatibility increase
Solution Approach 1:
The debug bridge serves as an intermediary that handles the complexity of tool compatibility and unified access requirements. It translates debug commands from the single host debugger into appropriate formats for different processor types, manages signal routing between the host and multiple processors, and abstracts the complexity from the user while concentrating it in the bridge circuitry where it can be managed systematically.
Data Source
AI summary
A field programmable gate array (FPGA) includes a soft processor and a soft processor debug unit implemented by programmable logic on the FPGA. The FPGA includes a system on a chip (SOC) that includes a hard processor and a hard processor debug unit. The FPGA includes a bus bridge, coupled to an input output (IO) of the FPGA, operable to transmit data between the IO and the soft processor debug unit and the hard processor debug unit.