FPGA DRAM Controller Self-Refresh Data Retention
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Reconfigurable computing systems face data corruption issues when reprogramming DRAM-based devices due to tri-stated inputs and outputs, which limits their use in applications like database processing and context switching, as existing solutions lack flexibility and require extensive data copying and restoration processes.
Innovation Solution
A system and method utilizing an FPGA-based DRAM controller in conjunction with a data maintenance block to maintain stable self-refresh command inputs, allowing for data preservation during reconfiguration by directing self-refresh commands and managing write/read timing windows, and storing data in a separate block for later retrieval.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If the FPGA is reprogrammed during live application, then the processor can be reconfigured for different tasks, but the DRAM data is corrupted due to tri-stated inputs and outputs
Solution Approach 1:
The patent applies preliminary action by initiating the self-refresh mode before the reconfiguration process begins. The memory controller detects the reconfiguration event and commands the DRAM to enter self-refresh mode in advance, preserving data integrity before the tri-state condition occurs. This preemptive measure ensures data is protected before the harmful tri-stated state affects the memory subsystem.
Solution Approach 2:
The patent introduces an intermediary mechanism (the memory controller's detection logic and control signals) that mediates between the reconfiguration event and the DRAM memory. The controller acts as a buffer, detecting the reconfiguration trigger and initiating the self-refresh sequence, thereby preventing direct data corruption from the tri-stated I/O condition.
2Ease of manufacture
If vendor provided memory controller IP is used, then design costs and project completion times are reduced, but flexibility to modify operating characteristics is limited
Solution Approach 1:
The patent applies dynamics by enabling the memory controller to dynamically respond to reconfiguration events. The controller detects reconfiguration triggers and automatically adjusts its operation by initiating self-refresh mode, providing adaptability to changing system states without requiring complete redesign of the controller IP. This dynamic behavior allows the system to adapt to reconfiguration scenarios while using vendor-provided IP cores.
Solution Approach 2:
The patent changes the operational parameters of the DRAM memory by transitioning it into self-refresh mode during reconfiguration events. This parameter change (from normal operation to self-refresh) allows the memory to maintain its data integrity while the controller is reconfigured, providing the necessary flexibility without modifying the core vendor IP design.
3Reliability
If the entire contents of DRAM data are copied and preserved in another part of the system, then data integrity is maintained, but the time required for reconfiguration becomes excessive
Solution Approach 1:
The patent extracts the data preservation function from the complex process of copying entire DRAM contents to another storage location. Instead, it utilizes the DRAM's built-in self-refresh capability, which maintains data integrity in-place without requiring external storage or data copying operations. This extraction of the preservation mechanism to the memory device itself dramatically reduces reconfiguration time.
Solution Approach 2:
The patent applies self-service by enabling the DRAM memory to maintain its own data integrity through self-refresh mode without requiring external intervention or data copying to other storage locations. The memory subsystem serves itself by automatically refreshing its contents during reconfiguration, eliminating the time-consuming data copy and restore operations that would otherwise be necessary.
Data Source
Figure 1
Figure 2
AI summary
A system and method for retaining dynamic random access memory (DRAM) data when reprogramming reconfigurable devices with DRAM memory controllers such as field programmable gate arrays (FPGAs). The DRAM memory controller is utilized in concert with an internally or externally located data maintenance block wherein the FPGA drives the majority of the DRAM input/output (I/O) and the data maintenance block drives the self-refresh command inputs. Even though the FPGA reconfigures and the majority of the DRAM inputs are tri-stated, the data maintenance block provides stable input levels on the self-refresh command inputs.