Digital Glitch Detection in Integrated Circuits Using FPGA Sampling
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Solution Overview
Problem
Existing glitch detectors in integrated circuits rely on analog components, which are costly, energy-intensive, and difficult to implement, making them inefficient in detecting glitches and vulnerable to hacker attacks.
Innovation Solution
A digital glitch detection method using a digital oscillatory signal generated from the electrical signal, with a clock signal that is insensitive to glitches, allowing for efficient detection and response to potential glitches through sampling value comparison.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If analog components are used for glitch detection, then detection capability is achieved, but development cost and time increase significantly
Solution Approach 1:
The patent replaces analog electronic components with a digital system using a Field-Programmable Gate Array (FPGA) to detect glitches. The digital system samples the power supply signal at multiple points and compares timing relationships between samples, eliminating the need for complex analog circuitry while maintaining glitch detection capability.
Solution Approach 2:
The patent creates multiple copies of the power supply signal through buffering and samples them at different time points. By comparing these copied and timed samples digitally, the system achieves glitch detection without requiring expensive and difficult-to-manufacture analog components.
2Reliability
If analog glitch detectors are implemented, then glitch detection is possible, but energy consumption increases causing heat release
Solution Approach 1:
The patent substitutes analog detection circuitry with a digital FPGA-based system that consumes less power. The digital sampling and comparison approach requires significantly less energy than traditional analog glitch detectors, reducing heat generation while maintaining detection reliability.
3Reliability
If analog components are used for detection, then glitch detection can be performed, but circuit space requirements increase
Solution Approach 1:
The patent replaces space-intensive analog components with a compact digital FPGA implementation. The digital sampling and timing comparison methodology achieves the same detection functionality in a much smaller footprint, freeing up valuable circuit board space.
4Measurement precision
If digital oscillatory signals are generated and sampled, then glitch detection accuracy improves, but system complexity increases
Solution Approach 1:
The patent uses an FPGA, which is a universal reconfigurable device capable of performing multiple functions. The same FPGA hardware is used for signal generation, sampling, timing measurement, and glitch detection, reducing overall system complexity despite the sophisticated detection algorithm.
Solution Approach 2:
The patent combines multiple functions (signal buffering, sampling, timing measurement, and glitch detection) into a single integrated digital system implemented on the FPGA. This merging of functions simplifies the overall system architecture while maintaining high detection accuracy through precise digital timing analysis.
Data Source
AI summary
A method for detecting at least one glitch in an electrical signal. This method comprises: generating, from said electrical signal, at least one digital oscillating signal which is sensitive to glitches; and—performing the following steps as a repeatable round: (a) assigning a time window to at least one digital oscillating signal; said time window being implemented on the basis of a clock signal substantially insensitive to said at least one glitch to be detected; (b) determining from said time window a sampling value of the digital oscillating signal, said sampling value being characteristic of said digital oscillating signal throughout its time window; (c) detecting any potential glitch in said electrical signal by comparing said sampling value with an expected reference value; and (d) outputting a response typifying a result of the comparison step. Also, a device for implementing said method is described.