FPGA Hardware Accelerator Blocks for ATE Testing
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Solution Overview
Problem
Conventional automated test equipment (ATE) systems are limited by the processing capabilities of the tester processor and bandwidth constraints, which restrict the number of devices under test (DUTs) that can be tested simultaneously, and require protocol-specific hardware bus adapter cards, making it inefficient to test DUTs with different communication protocols.
Innovation Solution
The solution involves distributing the command and test pattern generation functionality to Field-Programmable Gate Array (FPGA) devices, allowing each DUT to have a dedicated FPGA module that can generate and compare test patterns independently, and programming the communication protocol engine on FPGAs, enabling reconfigurability and eliminating the need for protocol-specific hardware.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If protocol-specific hardware bus adapter cards are used for each communication protocol, then the system can reliably test DUTs with different protocols, but the device complexity and hardware requirements increase significantly
Solution Approach 1:
The patent implements a universal FPGA-based protocol engine that can be reconfigured to support multiple communication protocols (PCIe, USB, SAS, SATA, etc.) through software programming rather than requiring separate dedicated hardware cards for each protocol. This allows a single ATE system to test DUTs with different protocols by loading different protocol-specific bitstreams onto the FPGA, thereby achieving protocol versatility without proportional hardware complexity increase
Solution Approach 2:
The patent changes the fundamental parameter of protocol implementation from fixed hardware to reconfigurable software-defined protocols on FPGA. By using bitstream programming, the system can dynamically change protocol characteristics without physical hardware modifications, transforming the ATE from a hardware-bound system to a software-flexible system that adapts to different communication standards
2Productivity
If the tester processor handles all command and data generation for multiple DUTs, then the system architecture remains simple, but the processing load and bandwidth requirements constrain the number of DUTs that can be tested simultaneously
Solution Approach 1:
The patent segments the testing functionality by assigning dedicated FPGA accelerator blocks to each DUT channel, separating the command generation and data processing tasks from the central tester processor. Each FPGA block independently handles commands and test data for its associated DUT, enabling parallel processing across multiple channels without requiring the tester processor to manage all DUTs sequentially, thus increasing productivity without excessive architectural complexity
Solution Approach 2:
The patent introduces FPGA accelerator blocks as intermediary components between the tester processor and the DUTs. These FPGAs act as dedicated intermediaries that receive commands from the tester processor and generate the necessary test patterns and data locally, reducing the processing burden on the tester processor and enabling more DUTs to be tested simultaneously by distributing the workload across multiple independent accelerator units
Data Source
AI summary
Automated test equipment (ATE) capable of performing a test of semiconductor devices is presented. The ATE comprises a computer system comprising a system controller communicatively coupled to a tester processor. The system controller is operable to transmit instructions to the processor and the processor is operable to generate commands and data from the instructions for coordinating testing of a plurality of devices under test (DUTs). The ATE further comprises a plurality of FPGA components communicatively coupled to the processor via a bus. Each of the FPGA components comprises at least one hardware accelerator circuit operable to internally generate commands and data transparently from the processor for testing one of the DUTs. Additionally, the tester processor is configured to operate in one of several functional modes, wherein the functional modes are configured to allocate functionality for generating commands and data between the processor and the FPGA components.