Incremental Compilation for FPGA Emulation Systems
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Solution Overview
Problem
Commodity FPGA-based emulators experience long compile turnaround times, which worsen with larger devices and increased FPGA system integration, making incremental design changes in VLSI circuit designs time-consuming and inefficient.
Innovation Solution
The implementation of incremental compilation for FPGA-based systems, where changes to a circuit design are simulated using a transactor on the FPGA, allowing the system to skip recompiling the entire design. This involves configuring the FPGA to use the transactor to simulate the changed portion of the circuit design, updating the compile database, and testing the design without full recompilation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If full recompilation is performed for every circuit design change, then compilation completeness is ensured, but compile turnaround time increases significantly
Solution Approach 1:
The patent divides the circuit design into modular components and segments the compilation process. Instead of recompiling the entire design, only the modified portions are recompiled and integrated with the previously compiled segments, maintaining compilation completeness while reducing overall compilation time.
Solution Approach 2:
The patent performs preliminary compilation of the entire circuit design before any modifications. This pre-compiled version serves as a foundation that can be efficiently updated through incremental changes, eliminating the need for complete recompilation and significantly reducing turnaround time while ensuring correctness through the established compilation framework.
2Productivity
If incremental compilation is used to reduce compile turnaround time, then time efficiency improves, but system complexity increases
Solution Approach 1:
The incremental compilation system is segmented into distinct functional modules including change detection components, selective recompiler, and integration manager. This modular structure manages system complexity by organizing the incremental compilation process into manageable, independent components that can be implemented and maintained separately.
Solution Approach 2:
The patent introduces intermediary data structures and compilation databases that mediate between the original design, modification inputs, and final compiled output. These intermediaries manage the complexity of tracking changes and coordinating incremental updates, providing a structured interface that simplifies the overall system architecture.
3Quantity of substance
If larger devices and FPGA system integration are used to improve performance, then emulation capacity increases, but compile turnaround time worsens
Solution Approach 1:
The patent segments the large-scale FPGA design into smaller compilable units or partitions. Each segment can be independently compiled and stored, allowing the system to leverage large FPGA capacity while avoiding the need to recompile the entire large design. When modifications occur, only affected segments are recompiled and reintegrated, maintaining both high emulation capacity and acceptable compilation time.
Data Source
AI summary
Embodiments of the present disclosure relate to a system and method for incremental compilation. The method includes identifying a change to a portion of a circuit design. The circuit design without the change was previously compiled to an FPGA. The method also includes configuring a transactor of the FPGA to simulate the portion of the circuit design with the change and configuring the FPGA to use the transactor to simulate the portion of the circuit design with the change.