FPGA Two-Level Interconnect Architecture Eliminates Bandwidth Limits
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Solution Overview
Problem
Existing cluster-based FPGA architectures face bandwidth limitations in interconnect schemes, particularly in two-level schemes, which restrict the number of unique signals that can be routed to logic cells, leading to inefficiencies and poor routability.
Innovation Solution
A two-level interconnect architecture with a higher number of first-level multiplexers compared to second-level multiplexers, allowing each logic cell input to have a unique signal, and employing depopulation schemes in both stages to minimize area and maximize routability, while avoiding bandwidth limitations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If a two-level interconnect scheme is used to save area, then area efficiency is improved, but input bandwidth is limited
Solution Approach 1:
The interconnect is divided into two levels: first-level multiplexers that aggregate routing tracks and second-level multiplexers that distribute to LUT inputs. This segmentation allows area reduction through hierarchical organization while maintaining bandwidth by ensuring the number of first-level multiplexers is sufficient to handle all required input signals without bottlenecking the signal flow to the logic cells.
2Quantity of substance
If a one-level interconnect scheme is used to avoid bandwidth limitation, then input bandwidth is improved, but area increases
Solution Approach 1:
The solution transitions from a flat one-level structure to a two-level hierarchical structure, adding a dimensional aspect to the interconnect organization. This hierarchical dimensioning allows the system to achieve both area efficiency and bandwidth requirements by distributing the routing function across two levels rather than requiring a single large-scale structure.
3Quantity of substance
If the number of first-level multiplexers is increased to eliminate bandwidth limitation, then input bandwidth is improved, but device complexity increases
Solution Approach 1:
The invention optimizes the parameter of first-level multiplexer count to a specific value that eliminates bandwidth limitation while controlling complexity. By carefully selecting the number of first-level multiplexers to match or exceed the number of required input signals, the system achieves full bandwidth utilization without requiring excessive multiplexers that would increase complexity and area.
Data Source
AI summary
An interconnect architecture for a programmable logic device comprises a plurality of interconnect routing lines. The data inputs of a plurality of first-level multiplexers are connected to the plurality of interconnect routing lines such that each interconnect routing line is connected to only one multiplexer. A plurality of second-level multiplexers are organized into multiplexer groups. Each of a plurality of lookup tables is associated with one of the multiplexer groups and has a plurality of lookup table inputs. Each lookup table input is coupled to the output of a different one of the second-level multiplexers in the one of the multiplexer groups with which it is associated. The data inputs of the second-level multiplexers are connected to the outputs of the first-level multiplexers such that each output of each first-level multiplexer is connected to an input of only one second-level multiplexer in each multiplexer group.