FPGA Interconnection Network Multiplexer Reduction
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Solution Overview
Problem
Existing interconnection networks in FPGAs are not well-suited due to being expensive in terms of size and delay, and have not kept pace with the evolving technology, particularly for the restricted interconnection problem, often being non-blocking and not optimized for FPGA designs.
Innovation Solution
A non-blocking routing network is designed using a multiplexer-based structure with reduced switch components, leveraging equivalent pin properties to optimize routing paths, allowing for the removal of switch components while maintaining network functionality, and implementing wide multiplexers to reduce signal delays and switching logic area.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If traditional interconnection networks are used in FPGAs, then routing robustness can be maintained, but the network size and signal delay become excessive
Solution Approach 1:
The interconnection network is divided into multiple routing rows, each handling specific routing functions. This segmentation allows the network to achieve robust routing capability without requiring a monolithic large-scale network, thereby reducing overall network size and signal delay while maintaining routing robustness through the distributed architecture of multiple specialized rows.
Solution Approach 2:
Each routing row is designed to handle multiple routing scenarios and can be configured for different routing paths. This multi-functionality allows the network to provide robust routing solutions for various configurations without requiring separate dedicated networks for each scenario, reducing the total network size while maintaining routing robustness through flexible resource utilization.
2Reliability
If routing robustness is prioritized in the interconnection network, then routing solutions remain reliable, but the network becomes expensive in terms of size and delay
Solution Approach 1:
The network is pre-configured with multiple routing rows that have predetermined routing capabilities. This preliminary structuring ensures that reliable routing paths are already in place before routing decisions need to be made, maintaining routing robustness while minimizing the time required to establish connections since the structural framework is already prepared.
Solution Approach 2:
The invention introduces a new dimensional approach by organizing routing resources into multiple rows that operate in parallel rather than relying on a single complex routing structure. This dimensional change provides redundant routing paths across different rows, ensuring routing robustness while reducing the time delay associated with traversing a single complex network path.
3Device complexity
If switch components are reduced to lower cost and complexity, then device area and power consumption decrease, but routing capability may be compromised
Solution Approach 1:
Multiple routing functions are merged into integrated routing rows that combine switching and routing logic. This merging reduces the total number of discrete switch components needed while maintaining comprehensive routing capability, as each routing row performs multiple functions that would traditionally require separate components, thereby reducing device complexity without sacrificing adaptability.
Solution Approach 2:
The routing rows are designed with dynamic configurability, allowing them to adapt their routing behavior based on current network conditions and requirements. This dynamic capability ensures that routing versatility is maintained even with fewer switch components, as the routing rows can reconfigure themselves to handle different routing scenarios efficiently.
Data Source
AI summary
A non-blocking routing network includes a plurality of external inputs and external outputs. Each row of a first plurality of routing rows provides a routing path from at least one of the external inputs to at least one of the external outputs and includes first through fourth multiplexers. Each row of a second plurality of routing rows provides a routing path from at least two of the external inputs to at least two of the external outputs. Each routing row of the second plurality of routing rows contains at least one less multiplexer relative to a routing row of the first plurality of routing rows, the one less multiplexer corresponding to at least two external inputs or two external outputs that are logically equivalent to one another.