FPGA Neural Network Classification via LSTM Resource Reuse
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Solution Overview
Problem
Existing neural network implementations on GPU and CPU-based systems are inadequate for embedded and portable applications due to stringent mechanical and power consumption requirements, necessitating the development of an FPGA device that can accurately predict performance and resource usage.
Innovation Solution
An FPGA method and device implementing a multi-level Recursive Neural Network with optimized partitioning of serial and parallel computations, using internal blocks and a real pipeline with registers to manage operations, and employing LSTM blocks with stored weights for efficient data processing, allowing for hardware resource reuse and compacted grid structures.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If neural networks are implemented on GPU- and CPU-based systems, then flexibility and ease of use are improved, but mechanical dimension and power consumption requirements are worsened
Solution Approach 1:
The patent replaces traditional CPU/GPU-based neural network implementations with an FPGA-based system. This substitution enables the deployment of LSTM networks in embedded and portable applications where power consumption and mechanical dimensions are critical constraints, while maintaining the necessary computational capabilities for sequence processing and classification tasks
2Use of energy by moving object
If neural networks are implemented on FPGA devices, then power consumption and mechanical dimensions are improved, but device complexity and development time are worsened
Solution Approach 1:
The patent applies parameter changes by configuring specific LSTM network parameters (number of layers, units per layer, learning rate, batch size) to optimize the balance between computational performance and hardware resource utilization on FPGA. This systematic parameter tuning enables efficient implementation while managing device complexity
Solution Approach 2:
The patent segments the neural network into distinct functional blocks (input layer, LSTM layers with gates, output layer) that can be independently configured and optimized on FPGA hardware. This modular segmentation simplifies the implementation process and enables precise control over resource allocation
3Productivity
If LSTM networks with multiple levels are used, then data processing capability is improved, but hardware resource requirements are worsened
Solution Approach 1:
The patent merges multiple LSTM layers and their associated gates (forget gates, input gates, cell gates, output gates) into an integrated FPGA implementation. By combining these functional elements and sharing common resources across layers, the system achieves high data processing capability while optimizing hardware resource utilization
Solution Approach 2:
The patent implements universal LSTM blocks that can be reused across multiple layers and configurations. The same hardware resources are used to perform different LSTM operations (forget gate computation, input gate computation, cell state updates) at different time steps and layers, maximizing resource efficiency while maintaining advanced processing capability
Data Source
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AI summary
The present invention relates to an IP Core FPGA, i.e., a system comprising a neural network capable of solving a whole class of problems related to deep learning. In particular, the IP Core solves classification problems based on sequences of data utilizing Recursive Neural Networks.