Cycle Accurate FPGA Memory Simulation via Protocol Separation
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Solution Overview
Problem
Simulating complex integrated circuits with Field Programmable Gate Arrays (FPGAs) faces challenges in maintaining cycle accuracy and reproducibility, particularly due to differences in memory types and the need for precise clocking and reset mechanisms, which complicates the debugging and validation of digital circuits.
Innovation Solution
The solution involves creating a cycle accurate and reproducible model of the device under test (DUT) memory by separating the DUT memory interface protocol from the target memory storage array, using a stoppable DUT clock and a free-running target clock, and employing hyper clocking to maintain a constant frequency and phase relationship, along with programmable address translation and initialization circuits to ensure cycle accuracy and reproducibility.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If DUT memory is mapped onto FPGA target memory with different memory types and interface protocols, then simulation speed is improved, but cycle accuracy is compromised
Solution Approach 1:
A memory interface protocol translator is introduced as an intermediary component between the DUT memory interface and the target memory. This translator handles protocol conversion and timing synchronization, allowing the FPGA to simulate different memory types while maintaining cycle-accurate behavior. The translator mediates the interface differences between various memory types (SRAM, DRAM, Flash) and the unified target memory architecture.
2Device complexity
If multiple memory types (SRAM, DRAM, Flash) are simulated on a unified target memory, then device complexity is reduced, but measurement precision of memory-specific behaviors is worsened
Solution Approach 1:
The system applies local quality by configuring the target memory with memory-type-specific parameters and behaviors at local regions. Different portions of the target memory can be configured to emulate SRAM, DRAM, or Flash characteristics through programmable control logic. This allows each simulated memory region to have the appropriate local properties (speed, volatility, access patterns) while using a unified physical memory substrate.
3Reliability
If clock frequency and phase relationships are strictly maintained for cycle reproducibility, then debugging capability is improved, but simulation flexibility is reduced
Solution Approach 1:
The clocking system is made dynamic through the use of programmable phase-locked loops (PLLs) and clock management logic. The clock frequency and phase relationships can be dynamically adjusted and reconfigured based on the simulation requirements. This allows the system to maintain strict cycle reproducibility when needed for debugging, while also allowing flexibility for different simulation scenarios and optimization levels.
Data Source
AI summary
A method, system and computer program product are disclosed for using a Field Programmable Gate Array (FPGA) to simulate operations of a device under test (DUT). The DUT includes a device memory having a number of input ports, and the FPGA is associated with a target memory having a second number of input ports, the second number being less than the first number. In one embodiment, a given set of inputs is applied to the device memory at a frequency Fd and in a defined cycle of time, and the given set of inputs is applied to the target memory at a frequency Ft. Ft is greater than Fd and cycle accuracy is maintained between the device memory and the target memory. In an embodiment, a cycle accurate model of the DUT memory is created by separating the DUT memory interface protocol from the target memory storage array.