FPGA On-Chip Network Architecture for High-Speed Interface Access
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Solution Overview
Problem
Traditional Field Programmable Gate Arrays (FPGAs) face challenges in handling high-throughput data communications due to the lower operating frequencies of user logic within the FPGA core, making it difficult to support high-speed interfaces like PCIe and GDDR6 memory effectively.
Innovation Solution
The implementation of an internal network-on-chip (iNOC) and external network-on-chip (eNOC) architecture provides low-latency and high-throughput access to high-speed IP interfaces, optimizing address decoding, data routing, arbitration, and flow control without consuming FPGA logic resources, allowing any node to issue read/write commands to any location within the device.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If traditional FPGA user logic is used for data communication, then the FPGA can be programmed and reconfigured, but the operating frequency is limited to 700 MHz which restricts high-speed interface support
Solution Approach 1:
The patent segments the FPGA architecture into two distinct domains: a high-speed network domain (operating at 2 GHz) for data communication and a programmable logic domain (operating at 700 MHz) for configuration and control. This segmentation allows each domain to operate at its optimal frequency without being constrained by the other, resolving the contradiction between programmability and operating speed.
Solution Approach 2:
The patent introduces an intermediary interface layer between the high-speed network domain and the programmable logic domain. This intermediary handles data translation and protocol conversion, enabling the slow programmable logic to control and reconfigure the fast network infrastructure without being limited by its own slower operating frequency.
2Speed
If high-speed interfaces like PCIe and GDDR6 are connected directly to FPGA core, then data transfer speed is improved, but congestion occurs in the FPGA core due to lower operating frequencies
Solution Approach 1:
The patent extracts the high-speed data communication functionality from the FPGA core and places it in a separate high-speed network domain. This extraction removes the source of congestion from the FPGA core, allowing the core to focus on programmable logic operations while the dedicated high-speed network handles data transfer at 2 GHz, thereby maintaining both high speed and high throughput.
3Adaptability or versatility
If more logic resources are used for routing and arbitration, then communication functionality is improved, but available resources for user logic decrease
Solution Approach 1:
The patent implements a simplified copy of routing and arbitration logic in the high-speed network domain that operates independently from the main FPGA logic resources. This copying approach allows the high-speed communication infrastructure to have its own dedicated control mechanisms, reducing the burden on FPGA logic resources while maintaining full communication functionality.
Data Source
AI summary
Methods, systems, and computer programs are presented for implementing a network on chip (NOC). One programmable integrated circuit comprises a plurality of clusters, an internal network on chip (iNOC), and an external network on chip (eNOC) outside the plurality of clusters. The plurality of clusters is disposed on a plurality of cluster rows and a plurality of cluster columns, each cluster comprising programmable logic. Further, the iNOC comprises iNOC rows and iNOC columns. Each iNOC row is configured for transporting data and comprising connections to clusters in a cluster row and the eNOC, and each iNOC column is configured for transporting data and comprising connections to clusters in a cluster column and the eNOC.