FPGA Overlay Emulation Reducing Compilation Time
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Solution Overview
Problem
Current FPGA-based emulation systems face significant challenges with long compilation times and high compute resource utilization due to the time-consuming place-and-route process for multiple FPGAs, which can take hours to days and require extensive CPU core usage.
Innovation Solution
Implementing FPGA overlay architectures that allow initial runtime emulation with slower performance initially, while concurrently compiling FPGAs, and gradually substituting finished FPGAs into the emulator, allowing for adaptive re-launching of non-overlay FPGAs to achieve better runtime performance, and using partial or different overlay architectures based on netlist content and critical timing paths.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If traditional place-and-route compilation is used for all FPGAs, then high runtime performance is achieved, but compilation time becomes extremely long (hours to days)
Solution Approach 1:
The patent applies preliminary action by pre-compiling overlay architectures onto FPGAs before runtime execution. The overlay architecture is compiled in advance and loaded onto the FPGA, allowing the system to start executing emulation tasks immediately without waiting for the full place-and-route compilation of the entire design. This preliminary preparation enables faster startup while the background compilation continues.
Solution Approach 2:
The patent segments the compilation process into two independent parts: overlay architecture compilation and place-and-route compilation. The overlay portion is compiled separately and can be loaded immediately, while the remaining place-and-route compilation proceeds in the background. This segmentation allows the system to achieve partial functionality quickly rather than waiting for complete compilation.
2Reliability
If traditional place-and-route compilation is used for all FPGAs, then complete design emulation is achieved, but compute farm resources are heavily utilized (thousands of CPU cores)
Solution Approach 1:
The patent applies partial action by implementing only the critical overlay architecture compilation initially, rather than compiling the entire place-and-route design at once. The overlay provides essential emulation functionality with reduced resource requirements. The remaining place-and-route compilation is performed gradually in the background, reducing peak compute farm utilization while still achieving complete emulation eventually.
3Loss of time
If FPGA overlay architectures are used initially, then compilation time is reduced and immediate emulation startup is enabled, but initial runtime performance is slower
Solution Approach 1:
The patent applies dynamics by making the system architecture adaptable and evolving over time. Initially, the system operates with overlay-only FPGAs providing faster startup. As place-and-route compilation completes for additional FPGAs, they are dynamically substituted into the emulation system, progressively improving runtime performance. The system transitions from a static overlay architecture to a dynamic hybrid architecture that optimizes performance over time.
4Productivity
If all FPGAs are compiled in parallel with place-and-route, then compilation throughput is maximized, but the worst-case FPGA still takes extremely long to compile
Solution Approach 1:
The patent applies skipping by allowing the emulation system to start execution immediately with overlay-only FPGAs, effectively skipping the lengthy place-and-route compilation step for initial runtime. The place-and-route compilation is performed in the background without blocking the startup process. This rushing through of the critical path enables immediate productivity while background compilation continues to maximize eventual throughput.
Data Source
AI summary
A system and a method are disclosed for emulating a design of an electronic circuit. One or more field programmable gate array (FPGA) overlays are programmed to implement a first set of logic elements of the design of the electronic circuit. A second set of logic elements of the design of the electronic circuit is implemented in one or more FPGAs. The FPGA overlays implementing the first set of logic elements and the FPGAs implementing the second set of logic elements are interconnected to each other. The design of the electronic circuit is then tested using the interconnected FPGA overlays and the FPGAs.