FPGA Clock Architecture for PCIE Homologous and Non-Homologous Modes

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Solution Overview

Problem

Existing domestic accelerating cards support only one of the homologous or non-homologous clock architectures for PCIE devices, leading to limitations in compatibility and requiring additional devices to adapt to different GPUs or accelerating devices, resulting in increased hardware costs and board space usage.

Innovation Solution

A clock architecture and method that includes a controller, GPU, PCIE switch, FPGA, clock generators, and fan-out devices, capable of generating and distributing both 100 MHz homologous and non-homologous clock signals, allowing the FPGA to read and select the appropriate clock signals based on the supported modes by the PCIE switch and GPU.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Adaptability or versatility

If a single accelerating card supports only one clock architecture (homologous or non-homologous), then the card design is simple, but compatibility with different GPUs and PCIE devices is limited

Engineering Contradiction:

ImprovecompatibilityVSAvoidcard design complexity

Core Design Contradiction:

Adaptability or versatilityVSDevice complexity

Solution Approach 1:

The accelerating card is designed to support both homologous and non-homologous clock architectures through a unified card structure. The card includes multiple clock input interfaces and a clock selection mechanism that can adapt to different GPU types, making a single card universally compatible with multiple device configurations rather than requiring separate specialized cards

Inventive Principle:

Principle #6Universality (Multi-functionality)

2Adaptability or versatility

If additional devices are added to adapt to different GPUs or accelerating devices, then compatibility is improved, but hardware costs and board space usage increase

Engineering Contradiction:

ImprovecompatibilityVSAvoidhardware quantity

Core Design Contradiction:

Adaptability or versatilityVSQuantity of substance

Solution Approach 1:

The patent merges the functionality of multiple specialized accelerating cards into a single unified card that can handle both homologous and non-homologous clock architectures. By integrating multiple clock input interfaces and a programmable clock selection mechanism within one card, the design eliminates the need for separate adaptation devices, reducing overall hardware quantity while maintaining compatibility

Inventive Principle:

Principle #5Merging (Combining)

Data Source

PatentUS12223560B2Clock architecture and method supporting PCIE clock, and medium

Publication Date: 2025.02.11 INSPUR SUZHOU INTELLIGENT TECH CO LTD

AI summary

A clock architecture supporting a PCIE clock, including a controller, a GPU, a PCIE switch, a FPGA, a first clock generator, a second clock generator, a first clock fan-out device and a second clock fan-out device; the first clock generator is configured to generate a 100 MHz homologous clock signal; the second clock generator is configured to generate a 100 MHz non-homologous clock signal; the FPGA is connected to the PCIE switch and the GPU, and configured to read clock architecture modes supported by the PCIE switch and the GPU, acquire corresponding 100 MHz clock signals according to the clock architecture modes, and fan out the acquired 100 MHz clock signals to the PCIE switch and the GPU to be used, the clock architecture modes are a homologous mode and a non-homologous mode.