Three-Port FPGA RAM Blocks for Soft Processor Register Files
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Solution Overview
Problem
Conventional FPGA memory blocks are poorly suited for use as register files due to their large size, synchronous operation, and lack of support for three ports, making it inefficient to construct register files for soft processors, which requires simultaneous reading and writing operations.
Innovation Solution
A three-port random access memory circuit block is designed for FPGA arrays, comprising two read-only ports and a synchronous write-only port, with programmable timing options to increase flexibility and optimize critical paths, minimizing circuit area and terminal count.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If conventional FPGA memory blocks are used for register files, then memory capacity is available, but the device complexity and area increase while simultaneously reading and writing becomes inefficient
Solution Approach 1:
The memory block is segmented into three independent ports: two read-only ports (A and B) and one write-only port (C). This segmentation allows simultaneous read operations from both ports A and B while a write operation occurs through port C, eliminating the need for complex arbitration logic and enabling efficient register file operations in soft processors
Solution Approach 2:
The memory block is designed with multi-functional capability to serve as a register file for soft processors. By providing three ports with independent control signals and timing options, the same memory block can efficiently handle multiple simultaneous operations (read from port A, read from port B, write to port C) that are essential for processor operations, rather than requiring separate dedicated circuits
2Adaptability or versatility
If conventional synchronous memory blocks are used, then timing control is simplified, but flexibility and optimization of critical paths are reduced
Solution Approach 1:
The memory block implements dynamic timing control by allowing each port to be independently configured as either synchronous or asynchronous. Read ports A and B can operate in asynchronous mode for maximum flexibility, while the write port C operates synchronously. This dynamic configurability enables optimization of critical paths without imposing uniform control complexity across all ports
3Quantity of substance
If large memory blocks are used for register files, then sufficient storage capacity is provided, but the area and resource usage become inefficient
Solution Approach 1:
The memory block is designed with local quality optimization by providing three ports with different functionalities (two read-only, one write-only) tailored to the specific requirements of register file operations. This localized optimization of port characteristics allows efficient use of memory capacity for register file purposes without requiring excessive area, as each port is specifically designed for its intended operation
Data Source
AI summary
A random access memory circuit adapted for use in a field programmable gate array integrated circuit device is disclosed. The FPGA has a programmable array with logic modules and routing interconnects programmably coupleable to the logic modules and the RAM circuit. The RAM circuit has three ports: a first readable port, a second readable port, and a writeable port. The read ports may be programmably synchronous or asynchronous and have a programmably bypassable output pipeline register. The RAM circuit is especially well adapted for implementing register files. A novel interconnect method is also described.