Coarse-Grain FPGA Routing Network for Deterministic High-Bandwidth Paths
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Solution Overview
Problem
Conventional FPGA routing fabrics face performance bottlenecks due to limited scalability and non-deterministic routing, which restricts bandwidth growth and increases power consumption, while fine-grain routing wires struggle to keep pace with increasing external interface bandwidth demands.
Innovation Solution
Incorporating a separate programmable deterministic coarse-grain routing network with pre-wired interconnects and fixed pipeline locations, allowing for guaranteed timing closure and efficient high-bandwidth data movement, alongside fine-grain routing wires, to address the limitations of traditional FPGA routing fabrics.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If conventional fine-grain routing wires are used, then routing flexibility is maintained, but bandwidth scalability is limited to 10-15% per generation
Solution Approach 1:
The routing network is segmented into two distinct layers: fine-grain routing wires for flexible local connections and coarse-grain routing network for high-bandwidth global connections. This segmentation allows each layer to specialize in its strength, resolving the contradiction between flexibility and scalability.
Solution Approach 2:
The patent introduces a new dimension of routing by adding coarse-grain channels that operate in parallel with fine-grain wires. This dimensional addition enables bandwidth scaling without compromising the flexibility of the original fine-grain routing layer.
2Device complexity
If conventional FPGA routing fabric is used, then device complexity is maintained, but power consumption increases due to non-deterministic routing
Solution Approach 1:
The coarse-grain routing network uses pre-wired deterministic paths with fixed pipeline locations, eliminating the need for runtime routing decisions. This preliminary action reduces dynamic power consumption associated with non-deterministic routing while maintaining manageable device complexity.
3Speed
If external interface bandwidth is doubled every 2-3 years, then interface performance is improved, but routing fabric becomes a performance bottleneck
Solution Approach 1:
The patent adds coarse-grain routing channels as a new dimension of data movement capability, enabling the routing fabric to scale bandwidth independently of the fine-grain layer and keep pace with external interface bandwidth growth.
Solution Approach 2:
The routing system dynamically selects between fine-grain and coarse-grain paths based on traffic requirements, allowing the fabric to adapt to varying bandwidth demands and maintain performance as interface speeds increase.
Data Source
AI summary
Circuitry is provided that includes programmable fabric with fine-grain routing wires and a separate programmable coarse-grain routing network that provides enhanced bandwidth, low latency, and deterministic routing behavior. The programmable coarse-grain routing network may be implemented on an active interposer die. The programmable fabric may be implemented on a top die that is stacked on the active interposer die. A protocol-based network on chip (NoC) may be overlaid on the coarse-grain routing network. Although the NoC protocol is nondeterministic, the coarse-grain routing network includes an array of programmable switch boxes linked together using a predetermined number of routing channels to provide deterministic routing. Pipeline registers may be interposed within the routing channels at fixed locations to guarantee timing closure.