FPGA Self-Test Structure Using Configuration Latches for Routing Paths
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Solution Overview
Problem
Testing of Field Programmable Gate Arrays (FPGAs) is complex due to the need for extensive test-vectors and silicon hardware, with existing methods being costly and dependent on EDA software, while also failing to adequately test routing paths which occupy a significant portion of silicon space and are susceptible to failure.
Innovation Solution
A self-test structure using existing device architectural resources, specifically SRAM-based configuration latches and look-up tables, is implemented to form scan chains at the reset state, allowing for pseudo-random sequence generation without software configuration, thereby testing logic blocks and routing paths independently of software.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If dedicated scan multiplexers and routing resources are added for each logic cell cluster, then testability is improved, but silicon space occupancy increases
Solution Approach 1:
The configuration latches are designed to serve dual purposes: normal device configuration during operation and scan chain formation during testing. By making the latches universal, dedicated test-only hardware is eliminated while maintaining full testability functionality.
Solution Approach 2:
The patent merges the configuration latch structure with the scan chain functionality. The same latches that configure the device logic are also used to store and shift test data, combining what were previously separate functions into a unified structure that reduces silicon space.
2Reliability
If programmable scan chain is activated through configuration of latches using software, then testing capability is provided, but dependency on EDA software increases and testing cannot occur without software programming
Solution Approach 1:
The scan chain is designed to self-configure automatically upon device reset without requiring external software intervention. The latches naturally form the scan chain structure when reset, enabling testing to proceed independently of EDA software toolsets.
Solution Approach 2:
The scan chain configuration is performed automatically during device reset before any user application is loaded. This preliminary self-configuration ensures testing capability is established without software dependency, allowing health checks and initial testing to occur immediately upon device power-up.
3Loss of information
If traditional DFT techniques are used to determine device status, then test information can be obtained, but tester time and complexity increase
Solution Approach 1:
The patent replaces complex mechanical tester operations with an automatic self-test mechanism. The scan chain automatically shifts test vectors through the logic elements and captures results, eliminating the need for extensive manual tester intervention and reducing testing time significantly.
Data Source
AI summary
A self test structure for interconnect and logic element testing in programmable devices including a plurality of logic elements; an interconnect structure for connecting the logic elements; SRAM based configuration latches for configuring the interconnect structure; test configuration circuitry for configuring any desired set of logic elements, interconnect structure and configuration latches during reset state that links the logic elements and interconnect structure to form a complete path between the interface points of the programmable logic device to enable testing of the desired elements in the complete path.