FPGA-SSD Pairing via Hardware Interface in Dense Servers
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Solution Overview
Problem
In densely populated server environments with multiple FPGA and SSD devices, existing technologies fail to establish clear pairings between these components, leading to data corruption and incorrect results due to the lack of physical association indicators, especially in virtualized environments where PCIe pass-through is enabled.
Innovation Solution
Implement a private hardware interface like System Management Bus (SMBus) between FPGA and SSD to share properties, update NVMe SSD firmware to accommodate acceleration attributes, and enhance manageability software modules to query and advertise pairing attributes, along with an API for identifying pairings.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If multiple FPGA and SSD devices are deployed in densely populated server environments, then device density and performance are improved, but the ability to identify and establish pairings between specific FPGA and SSD devices deteriorates
Solution Approach 1:
The patent introduces a hardware interface (such as SMBus) as an intermediary communication channel between FPGA and SSD devices. This intermediary enables direct exchange of pairing identification information, allowing the system to maintain pairing knowledge even when devices are densely populated and appear as separate physical functions in the host's PCI view.
2Adaptability or versatility
If PCIe pass-through is enabled in virtualized environments, then device functionality and performance are improved, but the visibility and identification of physical associations between FPGA and SSD devices deteriorates
Solution Approach 1:
The patent implements preliminary action by establishing hardware-level pairing identification mechanisms before virtualization is activated. The hardware interface records and maintains pairing information at the physical device level, ensuring that even when PCIe pass-through is enabled and devices appear as separate virtual functions, the original physical associations remain detectable through the pre-established hardware connection.
3Area of stationary object
If FPGA and SSD are packaged in one device enclosure for form factor benefits, then space efficiency is improved, but the clarity of physical function separation deteriorates
Solution Approach 1:
The patent applies segmentation by treating the FPGA and SSD as separate logical entities within the unified physical enclosure. The hardware interface enables distinct communication channels and identification mechanisms for each device, allowing the system to recognize and manage them as separate physical functions (PFs) while maintaining their physical co-location for space efficiency.
Data Source
AI summary
A system is disclosed. The system may include a Solid State Drive (SSD) and a co-processor. The SSD may include storage for data, storage for a unique SSD identifier (ID), and storage for a unique co-processor ID. The co-processor include storage for the unique SSD ID, and storage for the unique co-processor ID. A hardware interface may permit communication between the SSD and the co-processor.