FPGA Logic Template Switching for Real-Time Load Balancing
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Solution Overview
Problem
The inefficiencies in processing loads on Field-Programmable Gate Arrays (FPGAs) due to load imbalances and the time-consuming nature of rewriting circuit logics hinder real-time optimization in domain-oriented systems, leading to processing delays and reduced operational efficiency.
Innovation Solution
A control apparatus and method that utilizes an optimization apparatus to read and write pre-configured templates for circuit logics onto FPGAs, allowing real-time or near-real-time adjustment of processes to balance loads and improve processing efficiency by using a shared pool storage and templates stored in a logic pool.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If circuit logics are rewritten on FPGAs to optimize processing loads, then operational efficiency is improved, but the rewriting process is time-consuming and prevents real-time optimization
Solution Approach 1:
The patent applies preliminary action by pre-configuring multiple circuit logic templates before runtime. The control apparatus stores multiple pre-compiled circuit logic templates in memory, each optimized for different processing scenarios. When a rewriting is needed, the system simply switches to a pre-prepared template rather than performing time-consuming synthesis and placement operations at runtime, thus achieving real-time optimization without the usual time penalty.
Solution Approach 2:
The patent uses copying by creating multiple copies of circuit logic templates in advance. Instead of generating a single optimized circuit logic on-demand, the system creates multiple copies tailored to different load conditions and processing requirements. These copies are stored and can be rapidly switched between based on current operational needs, eliminating the need for time-consuming real-time synthesis and placement.
2Power
If synthesis and placement processes are performed to optimize circuit logics, then processing performance is improved, but the lengthy processes cause delays
Solution Approach 1:
The patent performs synthesis and placement operations in advance during template preparation phase, not during runtime. Multiple circuit logic templates are pre-optimized for different scenarios, storing the results in memory. When operational optimization is needed, the system simply selects and activates a pre-optimized template, achieving high processing performance without incurring synthesis and placement delays at runtime.
3Speed
If FPGAs are used for domain-oriented processing, then processing speed is improved, but design and manufacturing costs increase
Solution Approach 1:
The patent applies universality by designing a control apparatus that can dynamically reconfigure FPGAs to perform multiple different functions. Instead of manufacturing dedicated hardware for each specific application, the system uses a single FPGA device that can be programmed with different circuit logic templates to handle various processing tasks. This multi-functionality reduces design and manufacturing costs while maintaining high processing speeds through domain-oriented optimization.
Data Source
AI summary
A control apparatus includes a memory, and a processor coupled to the memory. The processor is configured to execute a process including reading, when information about a first process executed by a first circuit logic corresponding to a first template satisfies a given condition, a second template for a second circuit logic that executes a second process related to the first process from a storage area to obtain a read second template, the first circuit logic being set in a rewritable circuit area provided in a programmable logic circuit, the first circuit logic being implemented by writing the first template of which a circuit design synthesis has been completed and of which placement and routing have been already determined, into the circuit area; and writing the read second template into the circuit area to set the second circuit logic that executes the second process in the circuit area.