FPGA Test Unit for Parallel Signal Processing
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Solution Overview
Problem
Existing test apparatuses for semiconductor devices with analogue circuits are inefficient in processing multiple digital signals simultaneously, leading to prolonged test times and ineffective analysis of signal relations.
Innovation Solution
A test unit apparatus equipped with a hardware processing circuit, potentially configured on an FPGA, that processes multiple digital signals in parallel, including analogue-digital conversion and Fourier transform capabilities, to reduce processing time and enhance analysis efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of time
If digital signals are processed by software, then flexibility and adaptability are maintained, but processing time increases significantly
Solution Approach 1:
The patent replaces software-based signal processing with hardware-based processing using FPGAs and dedicated logic circuits. This substitution of mechanical/computational systems with hardware implementations dramatically reduces processing time while maintaining the necessary flexibility through programmable logic elements.
Solution Approach 2:
The patent creates parallel processing paths that can simultaneously process multiple digital signals. By implementing multiple processing channels in hardware, the system copies processing capabilities across different signal paths, enabling simultaneous analysis of multiple signals without sequential delays.
2Productivity
If multiple digital signals are processed individually, then processing accuracy is maintained, but total processing time increases
Solution Approach 1:
The patent merges multiple signal processing functions into a single integrated hardware circuit system. The FPGA-based processing circuit combines multiple processing channels, Fourier transform capabilities, and analysis functions into one unified hardware structure that can process multiple signals simultaneously through parallel operations.
Solution Approach 2:
The patent transitions from sequential one-dimensional processing to parallel multi-dimensional processing by implementing simultaneous processing of multiple signals across different channels. This dimensional expansion allows the system to handle multiple signals in parallel rather than sequentially, dramatically increasing throughput.
3Speed
If hardware processing circuits are used, then processing speed increases, but device complexity and cost increase
Solution Approach 1:
The patent employs dynamic reconfigurability through FPGAs, allowing the hardware processing circuit to be programmatically adjusted for different processing tasks. This dynamic capability provides hardware-speed processing while maintaining software-like flexibility, reducing the need for multiple dedicated hardware circuits for different functions.
Data Source
AI summary
In the digitizer, a plurality of ADCs convert a plurality of analogue signals output from the device to be tested, to digital signals, respectively. The processing circuit is configured as a software-independent circuit and processes a plurality of digital signals output from the plurality of ADCs. The processing circuit is formed on the FPGA. In the processing circuit, the FFT circuit performs complex Fourier transform on two digital signals.