FPGA Tester Board Routing for Multi-Standard DUT Sockets
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional automated test equipment (ATE) systems face limitations in processing load and bandwidth, restricting the number and types of devices under test (DUTs) that can be simultaneously tested. Additionally, these systems require hardware changes or special-purpose adapters to accommodate DUTs with different interface standards.
Innovation Solution
The proposed solution involves transferring command and test pattern generation functionality from the tester processor to field-programmable gate arrays (FPGAs), thereby reducing processing load and bandwidth requirements. This architecture also includes a connector module with routing logic that allows DUTs supporting different standards, such as U.2 and U.3, to be connected to the same socket without hardware changes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If command and test pattern generation functionality is transferred to FPGAs, then processing load and bandwidth requirements are reduced, but device complexity increases
Solution Approach 1:
The system divides functionality between the tester processor and FPGAs. The tester processor handles high-level test orchestration while FPGAs handle specific command and test pattern generation tasks. This segmentation distributes processing load and reduces bandwidth requirements between components.
Solution Approach 2:
FPGAs act as intermediary components between the tester processor and devices under test. They receive configuration from the processor and generate specialized test patterns, serving as a middle layer that reduces the processing burden on the main processor while maintaining test functionality.
2Adaptability or versatility
If hardware changes or special-purpose adapters are used to accommodate different interface standards, then adaptability is improved, but device complexity and ease of operation deteriorate
Solution Approach 1:
The system uses a universal connector module that can accommodate multiple interface standards (U.2, U.3, and other form factors) through a single socket. The FPGAs are configured with different protocol support to handle various interface standards, eliminating the need for multiple specialized hardware adapters.
Solution Approach 2:
The system changes operational parameters through FPGA configuration rather than hardware modification. By reconfiguring the FPGAs with different bitstreams, the system adapts to support different interface standards and protocols without physically changing the hardware connector or adapter.
3Productivity
If multiple DUTs are tested simultaneously, then productivity is improved, but processing load and bandwidth requirements worsen
Solution Approach 1:
The system segments the testing of multiple DUTs by assigning dedicated FPGAs to each device or group of devices. Each FPGA handles command generation and pattern creation for its assigned DUTs, distributing the processing load across multiple parallel processing units rather than overwhelming a single processor.
Data Source
AI summary
A method for testing DUT comprises receiving instructions from a system controller at a tester board, wherein the tester board comprises an FPGA and the tester processor are coupled to the system controller, and wherein the tester processor is operable to coordinate testing of a device under test (DUT). The method further comprises generating commands and data for testing the DUT and routing signals associated with the commands and the data in the FPGA based on a type of the DUT. Also, the method comprises transmitting the signals over lanes corresponding to a particular set of pins on the DUT, wherein the particular set of pins depend on the type of the DUT.