FPGA USB Interface Without CDR for 480 Mbps Data Recovery
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Solution Overview
Problem
Conventional FPGAs face challenges in handling high-speed USB 2.0 data transmission due to limited capabilities in device connectivity and the need for a CDR circuit, which restricts their ability to manage high-speed data rates effectively.
Innovation Solution
A system comprising a host and a device with an FPGA, featuring configurable logic blocks, a bus with P-channel and N-channel signals, and a USB interface with differential comparators, enables high-speed data communication by oversampling data signals with clock frequencies twice that of the data rate and a 90-degree phase shift, allowing for efficient data transmission without requiring a CDR circuit.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If conventional FPGA uses GPIO to handle USB data transmission, then low-speed and full-speed modes can be managed, but high-speed mode (480 Mbps) cannot be handled effectively
Solution Approach 1:
The invention segments the high-speed data transmission task into multiple parallel lower-speed channels. By using multiple GPIO pins to simultaneously transmit data bits that would normally require a single high-speed serial channel, the FPGA can achieve equivalent high-speed transmission using its existing GPIO capabilities, thus resolving the contradiction between speed and adaptability.
Solution Approach 2:
The invention merges multiple GPIO resources into a unified high-speed transmission interface. By combining the capabilities of multiple GPIO pins operating in parallel, the system achieves high-speed data transmission functionality without requiring dedicated high-speed serial interfaces, thereby maintaining adaptability across different USB modes while achieving high-speed performance.
2Speed
If FPGA deploys CDR circuit to handle high-speed USB mode, then data transmission capability is improved, but device complexity increases
Solution Approach 1:
The invention extracts the clock recovery and data sampling functionality from the traditional CDR circuit and implements it using the FPGA's existing programmable logic resources. By taking out the complex analog CDR circuitry and replacing it with digital logic implementations within the FPGA, the system achieves high-speed USB handling capability without adding external complex circuits, thus resolving the contradiction between speed and device complexity.
Solution Approach 2:
The invention creates a digital copy of the CDR functionality using the FPGA's programmable logic. Instead of implementing the traditional analog CDR circuit, the patent replicates its function through digital signal processing and timing recovery algorithms implemented in the FPGA's logic blocks, achieving the same high-speed data recovery capability with simpler, more integrated circuitry.
3Device complexity
If FPGA uses standard serdes without CDR, then device complexity is reduced, but ability to handle high-speed USB mode is compromised
Solution Approach 1:
The invention makes the serdes interface dynamic and adaptable by implementing programmable timing recovery and data sampling logic within the FPGA. This dynamic capability allows the simplified serdes to adjust its operation to achieve high-speed USB 2.0 compliance without requiring fixed, complex CDR circuitry, thus resolving the contradiction between device complexity and high-speed capability.
Solution Approach 2:
The invention changes the operational parameters of the serdes interface through programmable control within the FPGA. By dynamically adjusting timing parameters, sampling rates, and data recovery algorithms based on the detected USB mode, the simplified serdes achieves high-speed capability without the need for complex hardware, resolving the contradiction between simplicity and performance.
Data Source
AI summary
A system containing a host and a device having a field-programmable gate array (“FPGA”) is disclosed. The system includes a set of configurable logic blocks (“LBs”), a bus, and a Universal Serial Bus (“USB”) interface. The configurable LBs, in one aspect, are able to be selectively programmed to perform one or more logic functions. The bus contains a P-channel and an N-channel operable to transmit signals in accordance with a high-speed USB protocol. The USB interface is configured to include a first differential comparator operable to identify a logic zero state at the P-channel and a second differential comparator operable to identify a logic zero state at the N-channel.